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jliu_phd - Arithmetic and Control Components for an...

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Unformatted text preview: Arithmetic and Control Components for an Asynchronous System A THESIS SUBMITTED TO THE UNIVERSITY OF MANCHESTER FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN THE FACULTY OF SCIENCE AND ENGINEERING 1997 Jianwei Liu Department of Computer Science 2 Table of Contents 1 Introduction 17 2 Background 24 2.1 Introduction . ................................................................................ 24 2.2 Basic concepts . ............................................................................ 26 2.2.1 Delay models . ................................................................. 26 2.2.2 Circuit classification . ...................................................... 26 2.2.3 Hazards and races . .......................................................... 27 2.2.4 Metastability and arbitration . ......................................... 27 2.2.5 Circuit specifications . ..................................................... 28 2.2.6 Signalling protocols . ....................................................... 29 2.2.7 Data representation . ........................................................ 30 2.2.8 Synthesis . ........................................................................ 30 2.3 Sutherlands micropipelines . ....................................................... 31 2.3.1 Event control modules . ................................................... 31 2.3.2 Event-controlled storage element . .................................. 33 2.3.3 Micropipeline FIFO . ....................................................... 34 2.3.4 Micropipelines with processing . .................................... 35 2.4 The AMULET project . ................................................................ 35 2.4.1 AMULET1 chip . ............................................................ 36 2.4.2 AMULET2e chip . ........................................................... 37 2.4.3 AMULET3i . ................................................................... 38 3 Adder design 39 3.1 Introduction . ................................................................................ 39 3.2 Carry arbitration . ......................................................................... 40 3.2.1 Two-way carry arbiter . ................................................... 41 3.2.2 Three-way carry arbiter . ................................................. 44 3.2.3 Carry arbiters with more than three ways . ..................... 46 3.3 Parallel prefix computation . ........................................................ 47 3.4 Implementation . ........................................................................... 49 3.5 Refinement of the Manchester carry chain . ................................. 53 3.6 Simplification of carry select adders . .......................................... 55 3 3.7 Adder design for AMULET3i . .................................................... 57 3.8 Circuit design . .............................................................................. ....
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jliu_phd - Arithmetic and Control Components for an...

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