SOCA_5_ARM_Organization and Implementation

SOCA_5_ARM_Organization and Implementation - Chapter 5 ARM...

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Chapter 5 ARM Organization and Implementation Source: http://www.ece.uah.edu/~milenka 2 ARM organization ¾ Register file – ± 2 read ports, 1 write port + 1 read, 1 write port reserved for r15 (pc) ¾ Barrel shifter – shift or rotate one operand for any number of bits ¾ ALU – performs the arithmetic and logic functions required ¾ Memory address register + incrementer ¾ Memory data registers ¾ Instruction decoder and associated control logic multiply data out register instruction decode & control incrementer register bank address register barrel shifter A[31:0] D[31:0] data in register ALU control P C PC A L U b u s A b u s B b u s register
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Source: http://www.ece.uah.edu/~milenka 3 Three-stage pipeline ¾ Fetch ± the instruction is fetched from memory and placed in the instruction pipeline ¾ Decode ± the instruction is decoded and the datapath control signals prepared for the next cycle; in this stage the instruction owns the decode logic but not the datapath ¾ Execute ± the instruction owns the datapath; the register bank is read, an operand shifted, the ALU register generated and written back into a destination register Source: http://www.ece.uah.edu/~milenka 4 ARM single-cycle instruction pipeline fetch decode execute time 1 fetch decode execute fetch decode execute 2 3 instruction
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Source: http://www.ece.uah.edu/~milenka 5 ARM single-cycle instruction pipeline add r0,r1,#5 sub r2,r3,r6 cmp r2,#3 fetch time decode fetch execute add decode fetch execute sub decode execute cmp 1 2 3 Source: http://www.ece.uah.edu/~milenka 6 ARM multi-cycle instruction pipeline fetch ADD decode execute time 1 fetch STR decode calc. addr. fetch ADD decode execute 2 3 data xfer fetch ADD decode execute 4 5 fetch ADD decode execute instruction Decode logic is always generating the control signals for the datapath to use in the next cycle
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Source: http://www.ece.uah.edu/~milenka 7 ARM multi-cycle LDMIA (load multiple) instruction fetch decode ex ld r2 ldmia r0,{r2,r3} sub r2,r3,r6 cmp r2,#3 ex ld r3 fetch time decode ex sub fetch decode ex cmp Decode stage occupied since ldmia must continue to remember decoded instruction sub fetched at normal time but not decoded until LDMIA is finishing Instruction delayed Source: http://www.ece.uah.edu/~milenka 8 Control stalls: due to branches ¾ Branches often introduce stalls (branch penalty) ± Stall time may depend on whether branch is taken ¾ May have to squash instructions that already started executing ¾ Don’t know what to fetch until condition is evaluated
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Source: http://www.ece.uah.edu/~milenka 9 ARM pipelined branch time fetch decode ex bne bne foo sub r2,r3,r6 fetch decode foo add r0,r1,r2 ex bne fetch decode ex add ex bne Decision not made until the third clock cycle Two cycles of work thrown away if bne takes place Source: http://www.ece.uah.edu/~milenka 10 Pipeline: how it works ¾ All instructions occupy the datapath for one or more adjacent cycles ¾ For each cycle that an instruction occupies the datapath, it occupies the decode logic in the immediately preceding cycle ¾
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SOCA_5_ARM_Organization and Implementation - Chapter 5 ARM...

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