Srinivasan_thesis

Srinivasan_thesis - ARITHMETIC LOGIC UNIT (ALU) DESIGN...

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ARITHMETIC LOGIC UNIT (ALU) DESIGN USING RECONFIGURABLE CMOS LOGIC A Thesis Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering in The Department of Electrical and Computer Engineering by Chandra Srinivasan Bachelor of Engineering, Mysore University, 1997 December 2003
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ii To My parents and in loving memory of my grandmother
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iii Acknowledgements I would like to acknowledge certain people who have encouraged, supported and helped me complete my thesis at LSU. I am very grateful to my advisor Dr. A. Srivastava for his guidance, patience and understanding throughout this work. His suggestions, discussions and constant encouragement has helped me to get a deep insight in the field of VLSI design. I would like to thank Dr. M. Feldman and Dr S. Kak for sparing their time to be a part of my thesis advisory committee. I am very thankful to Electrical Engineering Department for supporting me financially during my stay at LSU. I take this opportunity to thank my friends Harish, Kavitha, Sajida, Sunitha and Anand for their help and encouragement. I would also like to thank all my friends here who made my stay at LSU an enjoyable and a memorable one. I extend a special thank-you to Srinivas, my constant companion and beloved friend. Last of all I thank the Almighty Lord for keeping me in good health and spirits throughout my stay at LSU.
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iv Table of Contents ACKNOWLEDGEMENTS. ............................................................................................ iii LIST OF TABLES. .......................................................................................................... vi LIST OF FIGURES . ........................................................................................................ vii ABSTRACT. .................................................................................................................... xi CHAPTER 1: INTRODUCTION. ................................................................................... 1 1.1 Literature Review. ........................................................................ 8 1.2 Chapter Organization. .................................................................. 14 CHAPTER 2: MULTI-INPUT FLOATING GATE MOSFET (MIFG MOSFET). ........ 15 2.1 Introduction. ................................................................................. 15 2.2 MIFG MOSFET Structure and Principle. .................................... 16 2.3 Multiple-Input Floating Gate CMOS Inverter. ............................ 21 2.4 Variable Threshold Voltage. ........................................................ 27 2.5 Unit Capacitance. ......................................................................... 34 2.6 Design Issues . .............................................................................. 36 CHAPTER 3: THE ALU DESIGN. ................................................................................. 39 3.1 The ALU Design and Operation. ................................................ 39 3.1.1 Multiplexer Design . ............................................. 39 3.1.2 Full Adder Design. ............................................... 41 3.1.3 ALU Design. ........................................................ 64 CHAPTER 4: DESIGN ISSUES, SIMULATIONS AND EXPERIMENTAL DATA .......................................................................................... 70 4.1 Multiplexer. ................................................................................. 70 4.2 Full Adder. .................................................................................. 76 4.3 Arithmetic Logic Unit. ................................................................ 79 4.3.1 Delay Measurements for 4-Bit ALU. ................... 88 CHAPTER 5: CONCLUSION AND FUTURE WORK. ................................................ 101 5.1 Future Work. ............................................................................... 101 BIBLIOGRAPHY .......................................................................................... 104 APPENDIX A: MOSFET MODEL PARAMETERS [35]. ............................................. 108 APPENDIX B: MOSFET MODELS PARAMETERS OF FABRICATED CHIP[35] . .109
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v APPENDIX C: SIMULATING FLOATING GATE MOS DEVICE . ............................ 110 VITA .......................................................................................... 116
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vi List of Tables 1.1 Number of additional gates and transistors required for different adder configurations[8]. ................................................................................................... 7 2.1 Variation in unit capacitance with respect to area and capacitance Note: C’ is the capacitance per unit area . .............................................................. 35 3.1 Truth table of a 4 to 1 multiplexer . ....................................................................... 48 3.2 Truth table of a 2 to 1 multiplexer . ....................................................................... 48 3.3 Truth table of a full adder . .................................................................................... 51 3.4 Truth table generated by inverters 1, 2 and 3 for SUM bit. .................................. 59 3.5 Truth table generated by inverter pair #1 and #4 for CARRY bit . ....................... 61 3.6 Truth table generated by inverter pair #5 and #6 for OR gate. ............................. 65 3.7 Truth table for the 4-bit ALU. ............................................................................... 69 4.1 Truth table of 4 to 1 multiplexer. ......................................................................... 73 4.2
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Srinivasan_thesis - ARITHMETIC LOGIC UNIT (ALU) DESIGN...

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