Analog Integrated Circuits and Signal Processing, 16, 299–304 (1998)
#
1998 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
Prediction of the Harmonic Distortion in Mosfet Gate Capacitors
MUHAMMAD TAHER ABUELMA’ATTI
King Fahd University of Petroleum and Minerals, Box 203, Dhahran 31261, Saudi Arabia
Received October 23, 1996; Accepted March 17, 1997
Abstract.
A Fourier-series model is presented for the capacitance-voltage characteristic of a MOS gate capacitor
using transistors biased in the strong inversion or the accumulation region. Using this model closed-form
expressions are obtained for predicting the harmonic distortion of the MOS gate capacitor driven by a large-
amplitude sinusoidal current. Results are compared with reported experimental observations.
Key Words:
harmonic distortion, MOS capacitors
Introduction
MOSFET transistors biased in strong inversion or
accumulation are widely used as capacitors in many
analog applications [1–4]. This is attributed to their
relatively large capacitance per unit area, better
matching and full compatibility with digital MOS
processes [5,6]. These capacitors, however, are
nonlinear and it is essential for designers to evaluate
the effect of this nonlinearity on the performance of
analog circuits incorporating MOS gates used as
capacitors.
Recently, Behr et al. [7] obtained the expression of
equation (1) for the total gate capacitance of a MOS
gate capacitor biased in either accumulation or strong
inversion.
C
0
g
±
C
0
ox
1
²
2
f
t
j
V
GB
²
V
x
j³
2
f
t
±²
´
1
µ
where
C
0
g
is the total small-signal gate capacitance per
unit area,
C
0
ox
is the oxide capacitance per unit area,
f
t
is the thermal voltage,
V
GB
¶
V
R
³
V
is the gate-to-
bulk voltage,
V
R
is the bias component of the gate-
to-bulk voltage,
V
is the signal component of the
gate-to-bulk voltage,
V
x
¶
V
FB
for the MOS gate
capacitor biased in accumulation region,
V
x
¶
V
T
for
the MOS gate capacitor biased in strong inversion,
V
FB
is the ﬂat-band voltage, and
V
T
is the strong
inversion threshold voltage. Equation (1) in its present
form can not yield closed-form expressions for the
harmonic distortion components of the gate-to-bulk
voltage resulting from driving the capacitor by a
current of the form
I
´
t
µ¶
I
o
³
I
p
sin
o
t
´
2
µ
Thus, using the ﬁrst three terms of the power series
expansion of (1), around the bias voltage
V
R
, Behr
et al. [7] obtained the expressions of (3) and (4) for the
second- and third-harmonic distortion respectively.
HD
2
±
f
t
V
1
2
´
V
R
²
V
x
µ
2
´
3
µ
HD
3
±
f
t
V
2
1
6
j
V
R
²
V
x
j
3
´
4
µ
where
V
1
is the amplitude of the fundamental
component of the gate-to-bulk voltage. By virtue of
their derivation, (3) and (4) are valid only for
relatively small values of
V
1
. In fact, the experimental
results reported by Behr et al. [7] show that for
V
pp
±
4 V, the difference between measured and
calculated harmonic distortions, using (3) and (4),
may be of the order of 20 dB. Thus, (3) and (4) cannot
provide a good estimate for the harmonic distortion of