hw6_solution - non-blocking or not. A. TSI is non-blocking....

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Question 1. In a 16x16 shared memory switch, the speed of each port is 1 Gbps. (a) Suppose the clock rate of the memory r/w is 50 MHz, find the width of the memory data bus. (b) If the memory has 32-bit of data bus, what is the minimum clock frequency? (c) If input-queue architecture is used to build the same switch, and the memory data bus has 32 bits, what is the minimum clock frequency of the memory r/w? A. (a) Required memory bandwidth is: 2x16x1 = 32 Gbps The bus width is 32Gbps/50MHz = 640 bits (b) 32 Gbps/32 = 1GHz (c) Required memory bandwidth is: 2x1 = 2Gbps The clock frequency is 2Gbps/32b = 62.5 MHz Questions 2. The definition of non-blocking in an NxN switch (N input, N output) is: Consider all the input-output connection requests, if each input port sends out at most one request and each output port receives at most one request, then all these connections can be established in the switch. Crossbar switching is non-blocking. Discuss if TSI (time slot interchange) architecture is
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Unformatted text preview: non-blocking or not. A. TSI is non-blocking. Given any kind of input-output connection requirements, we can write all slot data into the buffer and read out all of them to the output in each cycle. As a result, each cycle receives N slot data and delivers N slot data, there is no blocking. Question 3. The following architecture is a combination of TSI and crossbar, where each blue arrow is a TDM link. Discuss if it is possible to use a crossbar architecture plus multiplexers/de-multiplexers to build a switch and avoid the use of TSI? If yes, suppose each TDM link has four time slots (four user channels), draw a figure to show your design. A. Yes, it is possible. The solution is 1. Replace each TSI at input with a demultiplexer 2. Replace each TSI as output with a multiplexer 3. Replace the NxN crossbar with a NM x NM crossbar, where M is the number of slots we have for TDM. In the example, we use a 16x16 crossbar....
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