MCP-S11-05 - LECTURE 5 MEMORY ARCHITECTURE IN MULTICORE...

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Unformatted text preview: LECTURE 5 MEMORY ARCHITECTURE IN MULTICORE MACHINES NYU Multicore Programming Class, Spring 2011 lerner@cs.nyu.edu 1 2/28/2011 OS HW Memory hierarchy and hardware support for cache coherency application concurrency support Context Today well go over the memory architectural aspects of multicore chips. 2 NYU Multicore Programming, Spring 2011 2/28/2011 The false sharing problem Memory hierarchy Cache coherency problem Snooping protocols Atomic instructions F a l s e S h a r e H ie r a r c h y C o h e r e Todays agenda 3 e n c y S n o o p in g NYU Multicore Programming, Spring 2011 A t o m i c 2/28/2011 p P F a l s e S h a r e An (apparently) innocent parallel program 4 NYU Multicore Programming, Spring 2011 Count the elements in P that have a certain property. 2/28/2011 p P p/n A thread would test p/n elements and write the count to the F a l s e S h a r e An (apparently) innocent parallel program 5 NYU Multicore Programming, Spring 2011 Count the elements in P that have a certain property. n corresponding element in R. Q: Is this scalable? R 2/28/2011 speed up 1 F a l s e S h a r e A possible performance curve What is wrong? threads 1 6 NYU Multicore Programming, Spring 2011 2/28/2011 CPU size increase speed increase registers L1,L2, H ie r a r c h y us Memory hierarchy in a single processor main memory 7 NYU Multicore Programming, Spring 2011 bus 2/28/2011 CPU H ie r a r c h y cpu is notified cpu reads a value (load from memory) CPU interacts with the cache A cache hit. 8 NYU Multicore Programming, Spring 2011 2/28/2011 CPU H ie r a r c h y cpu reads a value (load from memory) Cache controller issues bus read Reading from memory If it is not already in cache, it is brought from memory. 9 NYU Multicore Programming, Spring 2011 a bus read 2/28/2011 CPU a full line is copied H ie r a r c h y cpu reads a value (load from memory) Cache controller issues bus read cpu is notified Reading from memory If it is not already in cache, it is brought from memory....
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MCP-S11-05 - LECTURE 5 MEMORY ARCHITECTURE IN MULTICORE...

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