MCP-S11-06 - LECTURE 6 MEMORY MODELS NYU Multicore...

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Unformatted text preview: LECTURE 6 MEMORY MODELS NYU Multicore Programming Class, Spring 2011 lerner@cs.nyu.edu 1 OS HW Memory consistency and barriers application concurrency support Context Today well continue talking about memory, specifically consistency. 2 NYU Multicore Programming, Spring 2011 Memory Consistency Models Instruction Reordering Memory Barriers (or Fences) R e o r d e r in g C o n s i s t e n c y B a r r ie Todays agenda 3 e r s NYU Multicore Programming, Spring 2011 If a program issues a read for a given memory position, what values can that read return? Intuitively, well say it is the last one Last can be easily determined in a uniprocessor case How about in the multiprocessor case? What is a memory consistency model? And why do we need one? NYU Multicore Programming, Spring 2011 4 CPU CPU CPU C o n s i s t e n c y Sequential Consistency Viewing memory as if one operation was done at a time. 5 NYU Multicore Programming, Spring 2011 A multiprocessor system is sequentially consistent if the result of an execution is the same as if the operations of all processors were executed in some sequential order, and the operations of each individual processor appears in this sequence in the order specified by its program [Lamport 79] C o n s i s t e n c y A Definition of Consistency Is it enough to guarantee correctness in the parallel shared-memory case? 6 NYU Multicore Programming, Spring 2011 Cache coherency protocols determine that a ( single ) write is eventually made visible to other processors writes to a same location appear in a same order to other processes Coherence of caches does not imply that writes to all locations appear in the same order Cache Coherence vs. Memory Consistency? No, the former does not guarantee the latter....
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MCP-S11-06 - LECTURE 6 MEMORY MODELS NYU Multicore...

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