EE331LE5rev6 - Experiment-5 Experiment-5 CMOS Timing,...

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Experiment-5 R. B. Darling EE-331 Laboratory Handbook Page E5.1 Experiment-5 CMOS Timing, Logic, and Memory Circuits Introduction The objectives of this experiment are to observe the operating characteristics of some CMOS timebase and memory circuits and to gain some practice in the design of CMOS combinatorial and sequential logic circuits. Precautions This experiment will use standard 4000-series (JEDEC B-series) buffered CMOS (metal gate) integrated circuits. These IC's have internal diodes to protect the MOSFET gates, but even so, they can still be destroyed by careless handling which may produce stray electrostatic discharge (ESD). Follow the same precautions as for dealing with a discrete MOSFET. To avoid static discharge damage to the IC, keep the part inserted into black conductive foam whenever it is not being used in a circuit. Alternatively, the pins may be pushed into a small piece of aluminum foil, or the part may be wrapped in the foil, if some conductive black foam is not available. Always discharge any built up static charges from your body by touching a grounded metal object, such as the frame of the lab bench, before handling the IC's. When finished with a given circuit, return the IC to the foam or the foil. Pay attention so that none of the leads become folded underneath the IC as you press it into the breadboard. If the leads on the IC are bent excessively outward so that they do not fit well into the breadboard, you can make the leads more parallel by rolling the IC on the tabletop to bend all of the leads on one side together. Exercise the same care when removing the IC from the solderless breadboard. Often, the IC may be held quite tightly by the breadboard, making removal difficult. Use a small screwdriver blade to pry the IC up from underneath in this case. If you choose to use just your fingers to pull the IC from the breadboard, be carefull that the IC does not flip around and stick its sharp leads into your finger. While humans normally kill IC's with static discharges, IC's themselves can bite back in this manner! (Usually this is non- fatal.)
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Experiment-5 R. B. Darling EE-331 Laboratory Handbook Page E5.2 Procedure 1 NAND and NOR gate truth table verification Set-Up Configure a DC power supply to output +5.0 Volts and verify this output with a bench DMM. Attach a lead to each output terminal. Insert a CD4001B (quad 2-input NOR gate) and a CD4011B (quad 2-input NAND gate) IC into a clear space on the solderless breadboard. With the breadboard groove running from left to right, insert the two IC's so that both indexed ends are towards the left. (The indexed end is the one with the dot, depression, or D-shaped cutout which identifies the pin 1 end of the package.) You will use the upper continuous line of tie points on the breadboard for the VDD = +5.0 Volt power supply bus, and the lower continuous line of tie points on the breadboard for the GND = 0.0 Volt power supply bus. For each of the two IC's use a jumper to connect pin 7 to the lower GND bus, and pin 14 to the upper VDD bus. Finally add two 0.1 µ
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This note was uploaded on 09/10/2011 for the course EE 331 taught by Professor Taicheng during the Winter '08 term at University of Washington.

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EE331LE5rev6 - Experiment-5 Experiment-5 CMOS Timing,...

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