quiz4solns

quiz4solns - Solution: 12 11 2 4000 2 <...

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CMPS 10 Fall 2007 Quiz 4 Solutions 1. (8 Points) Consider the following truth table with three inputs: a , b , and c . Inputs Output a b c x 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 a. (4 Points) Write a logical expression corresponding to the above truth table. Solution: c b a c b a c b a x + + = b. (4 Points) Draw a circuit containing only and , or , and not gates which corresponds to the expression you wrote in part (a). Solution: x a b c 2. (6 Points) a. (3 Points) Consider a memory unit whose memory address register is 28 bits wide. What is the maximum possible number of cells in this memory unit? Assume each cell is 1 byte wide, and give your answer in megabytes. Solution: 28 2 = 20 8 2 2 cells = 256 MegaBytes b. (3 Points) Consider a memory unit consisting of 4000 memory cells. What is the minimum possible width of the memory address register?
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Unformatted text preview: Solution: 12 11 2 4000 2 < < therefore the MAR must be at least 12 bits wide 3. (6 Points) Consider the following circuit with four inputs: 1 a , 2 a , 1 s , 2 s and output x , which is obtained by connecting the output lines of a 2-to-4 decoder to the input lines of a 4-input multiplexer. 00 1 a 01 10 x 2 a 11 1 s 2 s a. (3 Points) Describe its operation in words. Solution: If 1 1 s a = and 2 2 s a = then 1 = x , otherwise = x . In other words, this is a 2-bit compare for equality circuit. b. (3 Points) Describe its operation by filling out the truth table below: 1 a 2 a 1 s 2 s x 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 2 to 4 Decoder 4 Input Multiplexer...
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This note was uploaded on 09/15/2011 for the course CMPS 10 taught by Professor Tantalo during the Fall '08 term at UCSC.

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quiz4solns - Solution: 12 11 2 4000 2 <...

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