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Unformatted text preview: Chapter 10 Exercise Solutions E10.1 SPI is a synchronous protocol because there is a common clock signal synchronizes the transmitter and the receiver. E10.2 We need to program both the DDRD and the SPCR registers. We need to configure the SS, MOSI, SCK, & TxD pins for output and MISO and RxD pins for input. Write the value $3A into DDRD. For the SPCR register,- Bit 7 (SPIE): set to 0 to disable the SPI interrupt.- Bit 6 (SPE): set to 1 to enable the SPI function.- Bit 5 (DWOM): set to 0 to select normal CMOS pin.- Bit 4 (MSTR): set to 1 to select master mode.- Bits 3 & 2 (CPOL& CPHA): set to 01 to use falling edge to shift data in and out.- Bits 1 & 0 (SPR1 & SPR0): set to 01 to set the data rate to be 1/4 of the frequency of E clock. The following instruction sequence will set up the desired operation parameters: REGBAS equ $1000 ; base address of the I/O register block DDRD equ $09 ; offset of DDRD from REGBAS SPCR equ $28 ; offset of SPCR from REGBAS DDRD_in equ $3A ; value to initialize the DDRD register SPCR_in equ $55 ; value to initialize the SPCR register LDX #REGBAS LDAA #DDRD_in STAA DDRD,X LDAA #SPCR_in STAA SPCR,X E10.3 Connect the SPI pins as follows: SS pin : configured for output and is connected to the EN pin. SCK pin : configured for output and is connected to the CLK pin. MOSI pin : configured for output and is connected to the Din pin. Write the value $3A into the DDRD register to configure the desired pin directions. When simulating the SPI transfer, the most significant bit must be sent out first. Place the value $2B in accumulator A and use accumulator B as the loop count. REGBAS equ $1000 ; base address of the I/O register block DDRD equ $09 ; offset of DDRD from REGBAS SPCR equ $28 ; offset of SPCR from REGBAS PORTD equ $08 ; offset of PORTD from REGBAS DDRD_in equ $3A ; value to initialize the DDRD register LDX #REGBAS LDAA #DDRD_in ; configure port D pins 9- 1 STAA DDRD,X ; " BCLR SPCR,X $40 ; disable the SPI function LDAB #6 ; initialize the loop count to 6 LDAA #$2B ; place the data in A LSLA ; shift out the most significant two bits in A LSLA ; " loop6 BSET PORTD,X $10 ; set the SCK pin to high LSLA BCC set0 BSET PORTD,X $08 ; shift out 1 from the MOSI pin BRA shiftout set0 BCLR PORTD,X $08 ; shift out 0 from the MOSI pin shiftout BCLR PORTD,X $10 ; generate a falling edge on SCK to shift the bit on MOSI DECB BNE loop6 ... END E10.4 To read a byte from the HC589 #2, we need to set the OE input of this chip to low and all other HC589s to high. Configure the SPCR register as follows:- Bit 7 (SPIE): set to 0 to disable SPI interrupt- Bit 6 (SPE): set to 1 to enable the SPI function.- Bit 5 (DWOM): set to 0 to select normal port D pin....
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This note was uploaded on 09/12/2011 for the course EEL 4742 taught by Professor Weeks during the Spring '11 term at University of Central Florida.
- Spring '11