CH5 - ROM1 chip select The decoder design is diagrammed...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Rick Wagoner IET645 – Spring 2006 Chapter 5 Exercises E5-2. Write a byte into the INIT register to remap the SRAM and register blocks to $4000- $40FF and $C000-$C03F, respectively. INIT EQU $103D LDAB #$4C STAB INIT E5-3. How many memory chips are required to build a 1 MB, 32-bit wide memory system using the following SRAM chips? a. 256K x 1 SRAM chips 32 chips needed b. 256K x 4 SRAM chips 8 chips needed c. 64K x 8 SRAM chips 16 chips needed c. 128K x 16 SRAM chips 8 chips needed E5-5. Design an address decoder for a 68HC11-based product containing the following memory modules: ROM1: 4 KB SRAM1: 4 KB ROM1: 4 KB The reset vector is stored in ROM1. Assign the address space so that addresses $FFFE and $FFFF are covered by ROM1. We will use full address decoding with a 74139 chip. E1 will be tied to ground while A0-A1 will be tied to address bits A12-A13 respectively. Outputs 1Y1 will be tied to SRAM1 chip select, 1Y2 will be tied to ROM2 chip select, and 1Y3 will be tied to
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ROM1 chip select. The decoder design is diagrammed below. A13 A12 E1 A1 A0 1Y0 1Y1 1Y2 1Y3 E2 B1 2Y0 2Y3 2Y1 2Y2 B0 SRAM1_CS ROM1_CS ROM1_CS E5-7. Suppose that the address inputs A2-A0 of the 74138 decoder are connected in order to the address outputs A15-A13 of the 68HC11 and that the E3 input is connected to A12. E1 and E2 are tied to ground permanently. Determine the address ranges controlled by O0-O7. This scenario would control 8 ranges are listed below. Normally these 8 ranges would each be 8 KB in size. In this scenario they are each only 4 KB in size because the 12 address bit is used as the input enable control. This excludes all address where the 12 th bit is 0 or all of the ranges that begin with an even value. If the initial range is odd then the range is valid. O0 $1000 - $1FFF O1 $3000 - $3FFF O2 $5000 - $5FFF O3 $7000 - $7FFF O4 $9000 - $9FFF O5 $B000 - $BFFF O6 $D000 - $DFFF O7 $F000 - $FFFF...
View Full Document

This note was uploaded on 09/12/2011 for the course EEL 4742 taught by Professor Weeks during the Spring '11 term at University of Central Florida.

Page1 / 2

CH5 - ROM1 chip select The decoder design is diagrammed...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online