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Unformatted text preview: ROM1 chip select. The decoder design is diagrammed below. A13 A12 E1 A1 A0 1Y0 1Y1 1Y2 1Y3 E2 B1 2Y0 2Y3 2Y1 2Y2 B0 SRAM1_CS ROM1_CS ROM1_CS E5-7. Suppose that the address inputs A2-A0 of the 74138 decoder are connected in order to the address outputs A15-A13 of the 68HC11 and that the E3 input is connected to A12. E1 and E2 are tied to ground permanently. Determine the address ranges controlled by O0-O7. This scenario would control 8 ranges are listed below. Normally these 8 ranges would each be 8 KB in size. In this scenario they are each only 4 KB in size because the 12 address bit is used as the input enable control. This excludes all address where the 12 th bit is 0 or all of the ranges that begin with an even value. If the initial range is odd then the range is valid. O0 $1000 - $1FFF O1 $3000 - $3FFF O2 $5000 - $5FFF O3 $7000 - $7FFF O4 $9000 - $9FFF O5 $B000 - $BFFF O6 $D000 - $DFFF O7 $F000 - $FFFF...
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This note was uploaded on 09/12/2011 for the course EEL 4742 taught by Professor Weeks during the Spring '11 term at University of Central Florida.
- Spring '11