Final2 - What does the instruction TSX do? Copies the Stack...

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Unformatted text preview: What does the instruction TSX do? Copies the Stack Pointer register value to the X register. Copies the X register value to the Stack Pointer. Copies the Stack Pointer register value + 1 to the X register. Copies the Stack pointer register value — 1 to the X register. PHPP‘P’ What kind of addressing is used with the following instruction: LDAA $1234? a. Irmnediate ‘0. Direct c. Index (1. Extended Before execution the registers and memory locations have the values of: [$0000] = $42, [80001] = $41, [D] = $5342, and the carry bit is set to 1. What are the contents of the accumulator A after executing SBCA $0000: a. $10 b. $11 c. $12 (1. $13 In the 68HC11, what is the size of the following registers in the order of the: X, PC, A and P- (FLAGS): a. 8 bits, 16 bits, 8 bits, 16 bits b. 8 bits, 16 bits, 16 bits, 8 bits 0. 16 bits, 16 bits, 8 bits, 8 bits d. All are 16 bits. If the memory location at $00 contains SF 6 and the C flag is 1, what are the new values of this memory location and the C flag after the execution of ROL $00? a. 11110110 andCflagisl. b. 11101101 andCflagis 1. c. 01111011andCflagis 0. d. 11101101 andCflagis 0. If the address lines A15, A14, A13, A12, and All are used to address decode a blocks of memory 0 to 64K on the 68HC1 1 what size will be the decoded memory blocks? a. 2K block size b. 4K block size 0. 8K block size (1. 16K block size 7. If the E clock is running at lMHz and the given the following code, how long does it take to run the program from the label START to the label DONE (pick the closest answer)? DATA FDB $5000 START LDY DATA (5 clock cycles) LP DEY (4 clock cycles) CPY #551000 (7 clock cycles) BNE LP (3 clock cycles) DONE A total time of 40,960 microseconds A total time of 229,381 microseconds A total time of 409,605 microseconds A total time of 686,728 microseconds 9*? 9‘9” 8. What is the current flowing in the LED for the following circuit when (Y4 not) is a zero logic level (low)? 5 Volts V low = 1 volt V High = 5 volts A11 so (isb) €70 VD :2 V0“ A12 Sl A13 82 E 61 _ A14 g _m R —1000 A15 G3 a. 4.0 ma 1:). 3.0 ma 0. 2.0 ma d. 1.0 ma 9. One of the purposes of using bypass capacitors on power supply pins of a digital circuit is to: Increase the clock speed of the microprocessor. Filter the address bus to make address decoding easier. Filter the data signals to remove noise Filter the power supply signals to prevent noise from falsely triggering other digital devices. , ' 9.0.ch 10. The BSR instruction branches to a subroutine using an address field with a range of: a. -128 to +127. b. -127 to 128. c. O to 255. d. 0 to 65535. 11. How many memory chips are required to build a 16MB, 32 bit wide memory system using 1MB X 4 SRAM chips? a. 16. b. 32. i c. 64. d. 128. 12. 1f the crystal frequency of the 68HC11 is 4 MHZ, the E clock period is: a. 0.250 microseconds b. 0.500 microseconds c. 1.000 microseconds d. 2.000 microscconds 13. Data Do u D7 bits are valid from the 68HC11 to an external device on Port C only when: R/(Wnot)=1 andE= 1. R/(W not) : 0 and E = 0. R/(W not): 1 andE=0. R/(Wnot)=0andEzl. 9.0 9‘9: 14. To save external pins on the 68HC11, which statement is true? The SP1 and SCI are shared with port E. The SP1 and SCI are shared with pelt D. The upper and the lower eight bits of the address bus are multiplexed together. The data bus and the upper eight bits of the address bus are multiplexed together. 999‘s 15. What kind of memories use a capacitor store a bit of data and also must be refreshed periodically? a. Static memories. b. Slow memories. c. Non—volatile memories. d. Dynamic memories. 16. Which of the following is true for separate 1/0 as compared to memory mapped I/O? a. U0 devices have their own address space that is Separate from the main memory address space and are accessed using special I/O instructions. b. Microprocessors must have dedicated instructions for performing arithmetic operations on input and output devices. c. 1/0 is treated the same as any other memory location and there is no difference between memory and I/O. (1. Special addressing registers are needed for all I/Q operations that access memory. 17. What is the minimum number of 7415138 (3-to 8) de-multiplexers that will be needed to address two external 8 KB by 8 bit SRAM chips, and one 8 KB by 8 bits flash memory? The two 8 KB by 8 bits EPROM chips start at memory locations $8000 and $A000 and the 8 KB by 8 bits flash memory starts at address $0000. a.1 b2 c.3 d.4 18. The software interrupt instruction SW1 uses what 2 two locations in memory to store its vector address? a. $FFFE and $FFFF. b. $FFFC and SFFFD. C. $FFF6 and $FFF7. d. $FFF5 and $FFF6. 19. Given the following 74LSl 38 address decoder (Y4 not) goes low for which addresses: A13 so (lsb) Y0 A12 81 All 82 E 9.} A14 G2 __ A15 a $0000 - $07FF $0800 - $0FFF $1000 — $17FF $1800 — $1FFF 9.0.65» 20. In 68HC1 l, which one of the following port(s) is/are used for the address bits AO-A7? a. Port F. b. Port B. 0. Port C. d. Port E. 21. In Mode zero of the 8255 there are how many I/O bits available? 4. 6. 99cm 22. Which of the 6850 registers are for writing? a. Receive data and configuration. b. Transmit data and status. 0. Receive data and status. (1. Transmit data and configuration. 23. The time required to transmit 4000 characters of 8 bits using RS 232C with a format of 8 data bits, 1 start bit, lstop bit and no parity with a transmit speed of 9600 baud is: a. 1.04 see b. 2.08 see c. 4.167 sec. d. 5.22 sec. 24. The voltag= level used for EIA-RS232C is: a. +. - Y (Y is between 3 and 15 volts). b. -?- V (Y is between 3 and 15 volts). 0 V O7 is betvreen 0 and 5 volts). d +./- V (V is between 0 and 10 volts). 25. A reason that a parity error can occur in RS232C is when: a. the number of bits received is same as what was transmitted. b. an odd number of l ‘s were transmitted but an even number of 1’s were received. c. data was not read from the receive buffer at a fast enough rate. (1. data is sent to transmit buffer faster than it can being sent serially. 26. For RS232, the maximum allowable difference in baud rates between the receiver and transmitter can be: a. +/— 2%. b. +/- 3%. c. +/~ 4%. d. +/— 5%. 27. It is desired to place an output port at address $7E08. Full address decoding is desired and the address decoder chosen is a 16 input NAND GATE that is used to decode the address $71308. How many inverters will be needed for input to this NAND GATE? a8 b. 9 c. 13 d. 16 28. What part is best suited to be used as an output port to transfer 8 bits of data from the 6BCH11? a. 74LS373 b. 7415138 c. 74LSZ44 d. 74LSOO 29. If the reg. SP : $12FB, then the instruction PSHY retrieves data from the Y register and places this value on the stack and sets the SP register to: a. $12FD. b. $12FC. c. $12FA. d. $12F9. 30. Given a memory device connected to the 68HC11, to minimize ringing on the address and data buses: F” Big capacitors should be placed on the data and address signals of these buses. b. Proper impedance termination (of all interconnects) must be maintained between all connections on the address and data signals of these buses. c. The address and data lines should run as fast as possible and if possible using parts with the fastest rise times. d. iOO meg-ohm resistors should be placed between the memory and the 68HC11 to isolate the memory device from the 68HC1 I . ...
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Final2 - What does the instruction TSX do? Copies the Stack...

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