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Experimento1_2011

Experimento1_2011 - LABORATRIO DE ARQUITETURA DE...

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LABORATÓRIO DE ARQUITETURA DE COMPUTADORES Experimento 1 Unidade Lógica Aritmética 2011
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SUMÁRIO 1 Introdução teórica ............................................................................................................... 1 2 Procedimento Preparatório .................................................................................................. 1 3 Experimento ........................................................................................................................ 2 4 Resultados ........................................................................................................................... 2
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1 1 Introdução teórica A unidade lógica e aritmética é responsável por realizar as operações sobre os registradores em um microprocessador. As operações ocorrem durante o estágio de execução da instrução. O MIPS possui um conjunto de instruções lógicas, neste experimento iremos descrever em VHDL a ULA do processador MIPS com um conjunto básico de instruções. A estrutura lógica da ULA a ser descrita é mostrado na Figura 1, a Tabela 1 mostra os sinais de controle necessários para realizar cada operação. Figura 1 Estrutura Lógica da ULA do MIPS Simplificado Tabela 1 Sinais de Controle e Operações do MIPS Simplificado Código Operação 000 AND 001 OR 010 Soma 110 Subtração 111 SLT (Set if Less Than) 2 Procedimento Preparatório
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