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FINALF04_ANS

# FINALF04_ANS - 1 McGill University Faculty of Engineering...

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1 McGill University DIGITAL SYSTEM DESIGN Faculty of Engineering ECSE-323 FINAL EXAMINATION FALL 2004 (DECEMBER 2004) STUDENT NAME McGILL I.D. NUMBER Examiner: Prof. J. Clark Associate Examiner: Prof. Frank Ferrie Signature: Signature: Co-Examiner: Prof. M. Marin Signature: Date: December 20 , 2004 Time: 2:00 pm INSTRUCTIONS: SEE NEXT PAGE.

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3 (5 points) a) Write the logic function produced by the following transmission gate circuit. (5 points) b) Draw the equivalent CMOS circuit showing clearly the PULL-UP-NETWORK and the PULL-DOWN-NETWORK. _________________________________________________________________________________________ a) Z = f8e5 A [ f8e5 B C + B f8e5 C ] + A [ f8e5 B f8e5 C + B C ] = A B C.

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Your Name__________________________________________________________________________________ Question 2 :Boolean Logic Theory (15 points) Find h = h(x 1 ,x 2 ) such that the following network structure can produce the function f (x 1 ,x 2 ,x 3 ,x 4 ) = Σ m (1,2,5,6, 9,10,12,15) G H X 1 X 2 X 4 X 3 h f (5 points) a) Give the algebraic expression of f. (5 points) b) Give the algebraic expression of h. (5 points) c) Give the minimal sum-of-products logic circuits corresponding to H and G. _________________________________________________________________ 4
Your Name______________________________________________________________________________ Question 3 : VHDL (20 points) a) (10 points) Using a single selected signal assignment statement, write a complete VHDL description of a circuit that implements the Boolean function f (x,A,B)= [x(0)x(1) + x(0)A +x(1)B]. Use x(0) and x(1) as the select inputs. Draw the equivalent multiplexer circuit.

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FINALF04_ANS - 1 McGill University Faculty of Engineering...

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