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FINALw07-ANS

# FINALw07-ANS - 1 McGILL UNIVERSITY Electrical and Computer...

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Your Name_______________________________________________________ Question 1 : CMOS Circuit Technology (10 points) Draw a CMOS circuit that produces the same function as the circuit shown below A B C F ONLY TRUE VARIABLES ARE AVAILABLE AS INPUTS HINT: Only 8 transistors are required. Remark: A correct solution with more that 8 transistors will receive partial credit. ________________________________________________________________________ ANSWER f8e5 F (A,B,C) = f8e5 A + B C ; F =A ( f8e5 B + f8e5 C ) A F B C C B Vdd 2
Your Name_______________________________________________________ Question 2 :Boolean Logic Theory (15 points) (7 points) a) Which of the following are self-dual functions F = x y ; G = f8e5 x ; H = x y z + f8e5 x y + f8e5 x f8e5 y z. (8 points) b) Draw a circuit producing the function F(A,B,C,D) = f8e5 C f8e5 D + f8e5 A f8e5 B f8e5 D + f8e5 A B D + C f8e5 D B + C f8e5 D f8e5 A Using ONLY a minimal number of 2 x 1 MUX’s. ________________________________________________________________________ ANSWER (a) F = x y, F D = x + y , F F D ,therefore, F is not self-dual. G = f8e5 x , G D = f8e5 x, G = G D ,therefore, G is self-dual. H = x y z + f8e5 x y + f8e5 x f8e5 y z, H D = (x + y + z)( f8e5 x + y)( f8e5 x + f8e5 y + z) = (x + y + z)( f8e5 x + yz) = xyz + f8e5 xy + z f8e5 x + yz xy z 00 01 11 10 0 0 1 0 0 1 1 1 1 0 Map of H Map of H D H = H D , therefore, H is self-sual. xy z 00 01 11 10 0 0 1 0 0 1 1 1 1 0 3

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Continue Part (b) on next page…. Your Name_______________________________________________________ Question 2 :Boolean Logic Theory (CONTINUES) (b) We apply the Shannon expansion repeatedly until the residue functions are input variables or fixed polarities. The choice of expansion variable is arbitrary and produces different, although correct, solutions. Expansion with respect to A : F(A,B,C,D) = f8e5 A [ f8e5 C f8e5 D + f8e5 B f8e5 D + B D + C f8e5 D ] + + A [ f8e5 C f8e5 D + C f8e5 D B] Residue functions expansion with respect to B: R0 = [ f8e5 D + f8e5 B f8e5 D + B D ] = f8e5 B [ f8e5 D ] + B[ 1 ] R1 = [ f8e5 C f8e5 D + C f8e5 D B ] = f8e5 B[ f8e5 C f8e5 D ] + B[ f8e5 D ] R10 = [ f8e5 C f8e5 D ] Expanding R10 with respect to C: R10 = f8e5 C[ f8e5 D ] + C[ 0]. The resulting circuit is the following: 4 2 x 1 MUX 2 x 1 MUX 2 x 1 MUX 2 x 1 MUX B D C B F A 0 1 R0 R1 R10
Your Name_______________________________________________________ Question 3: VHDL (20 points) (10 points) a) Using a single selected signal assignment statement write a complete VHDL description of a circuit that implements the Boolean functions: Y(1)=XYZ+W Y(2)=WXY+Z Y(3)=X+Y (10 points) b) Using a single process block write a complete VHDL description of a circuit that takes in two 1-bit signals (X and Y) and, on a positive-going clock edge, increments a count value if X and Y have the same value and decrements the count value otherwise. Assume that COUNT represents an 8-bit signed number. If the COUNT value is at its minimum, then do not

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