Alexander - LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS...

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4/20/2006 ELEC7250: Alexander 1 LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION
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4/20/2006 ELEC7250: Alexander 2 PROBLEM STATEMENT To write a logic simulator to verify combinational circuits given a set of input vectors and the expected output responses. To introduce a design error in the circuit and list the failing vectors and primary outputs where the errors are observed. To diagnose the design error.
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4/20/2006 ELEC7250: Alexander 3 Logic Simulation. Each PI , PO and gate were represented as a structure ( node). PI’s , PO’s contained information like name, input vector values , expected response respectively. Gate nodes also contained the fan-in list, fan-out list etc. Simple search method was used to find out the fan- out connections to their respective gates.
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4/20/2006 ELEC7250: Alexander 4 START Read input, output and gate data from simulation file into the structures. Initialize gate fan-in’s and fan-
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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Alexander - LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS...

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