Anbumony - A Robust Logic Simulator Using Robust Dynamic...

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20 April 2006 VLSI Testing-Final Project Presentation 1 A Robust Logic Simulator Using A Robust Logic Simulator Using Dynamic Levelization Dynamic Levelization Kasi L. K. Anbumony Dept. of Electrical Engineering Auburn University, AL – 36849 USA
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20 April 2006 VLSI Testing-Final Project Presentation 2 Motivation for This Work Logic simulator to verify combinational circuits in bench circuit description language. Logic simulator to handle unlevelized netlists. Logic simulator to handle hierarchical netlists. Using Logic simulator as Fault simulator with the help of combinational ATPG & AUSIM. Gaining popularity to simulate, verify the functionality and diagnose design faults in netlists.
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20 April 2006 VLSI Testing-Final Project Presentation 3 Outline Definition Data structure & Algorithm Complexity Dynamic Levelization Results for Logic Simulator Diagnosis Fault Dictionary Algorithm Atalanta & AUSIM Simulation & Discussion Conclusions
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20 April 2006 VLSI Testing-Final Project Presentation 4 Logic Simulator • True value simulator that computes the responses for a given stimuli • Used for design verification • Supports AND, OR, NOT, BUFF, NAND, NOR, XOR, XNOR for any number of fan-ins • Two methods have been tried to optimize the CPU time
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20 April 2006 VLSI Testing-Final Project Presentation 5 Data structure: Used Dynamically growing array with each net having two properties: name and their logic value netname netvalue
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20 April 2006 VLSI Testing-Final Project Presentation 6 Algorithm in detail: Flowchart Start Read the input and output netnames netnameI+netnameO Assign values to input nets netvalueI Inputs are assigned logical values (2^N) while ! (EOF(*.bench)) Input netsof given gate ==netnameI?
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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Anbumony - A Robust Logic Simulator Using Robust Dynamic...

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