Grimes - Logic Simulator for Hierarchical Bench Hillary...

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Unformatted text preview: Logic Simulator for Hierarchical Bench Hillary Grimes III – Term Project ELEC 7250 – Spring 2006 4/20/2006 ELEC7250 Project: Grimes 1 Problem Statement Develop a Logic Simulator for Zero­Delay Boolean gates to perform circuit verification. Inputs: ­­Hierarchical Bench Circuit Description ­­Input Vectors and Expected Outputs Outputs when Simulation Fails: ­­Inputs and Outputs with failed responses ­­Diagnosis Information 4/20/2006 ELEC7250 Project: Grimes 2 Circuit Representation in C Each hierarchical block is stored as an element in a block array containing: ­­block name ­­array of gates ­­input signal list ­­output signal list Gates Contain: ­­gate name ­­gate type ­­level ­­input signal list ­­output signal list ­­fan in array 4/20/2006 Signals Contain: ­­signal name ­­level ­­value ELEC7250 Project: Grimes 3 Building the Block Array Each block is flattened as it is read in After POs and PIs are assigned, the gate array is built. Each line from the netlist is either a boolean gate, or a previously defined block. ­If boolean gate – add to gate array ­­gate name: “g0, g1, g2, etc” ­­assign input and output signals ­If not boolean – insert block from previous elements in block array 4/20/2006 ELEC7250 Project: Grimes 4 Insert Gates for an XOR Block XOR Description: Inputs: A, B Output: Y X1=NAND(A,B) X2=NAND(X1,A) X3=NAND(X1,B) Y=NAND(X2,X3) XOR Block’s gate array contains: g0: NAND g1: NAND Inputs: A, B Inputs: X1, A Output: X1 Output: X2 g2: NAND g3: NAND Inputs: X1, B Inputs: X2, X3 Output: X3 Output: Y OUT = XOR ( IN_1, IN_2) Inserts Gates: XOR0.g0: NAND XOR0.g1: NAND Inputs: IN_1, IN_2 Inputs: XOR0.X1, IN_1 Output: XOR0.X1 Output: XOR0.X2 XOR0.g2: NAND XOR0.g3: NAND Inputs: XOR0.X1, IN_2 Inputs: XOR0.X2, XOR0.X3 Output: XOR0.X3 Output: OUT 4/20/2006 ELEC7250 Project: Grimes 5 Level Block Gates are inserted into gate array such that each gate’s inputs are either PIs, or an output of a previous gate. To levelize a block, we visit each gate in increasing order: ­­level of gate = max level of input signals ­­level of gate’s output = 1+gate level ­­increasing order ensures that each input has an assigned level 4/20/2006 ELEC7250 Project: Grimes 6 Simulation To simulate a block given an input vector: ­­assign signal values to primary inputs ­­visit each gate in gate array (increasing order): ­evaluate and assign gate’s output signal Diagnose if output differs from the expected response ­­diagnoses starts at each failing PO and back tracks through the circuit ­­information (including signal values) for each gate along a path to the failing PO is printed 4/20/2006 ELEC7250 Project: Grimes 7 Circuit c17 Number of Inputs Number of Outputs Execution Time (msec) 6 5 2 0 c432 120 36 7 63 c499 162 41 32 141 c880 320 60 26 110 c1355 506 41 32 172 c1908 603 33 25 250 c2670 872 233 140 438 c3540 1179 50 22 485 c5315 1726 178 123 797 c6288 2384 32 32 781 c7552 4/20/2006 Number of Gates Results 2636 207 108 1125 ELEC7250 Project: Grimes 8 Results Execution Times for ISCAS85 Circuits 1200 c7552 Time (msec) 1000 c5315 800 c6288 600 c2670 400 200 c17 c432 c499 c1355 c880 c3540 c1908 0 Circuit 4/20/2006 ELEC7250 Project: Grimes 9 Conclusion Execution times seem to grow with both the number of gates, and the number of inputs/outputs Diagnosis still needs work ­­if multiple paths to the failing PO include the same gate, that gate’s information is printed multiple times. ­­diagnostic resolution could be much better with a better algorithm 4/20/2006 ELEC7250 Project: Grimes 10 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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