Hill - Brad Hill ELEC 7250 Logic Simulator 4/25/2006...

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Unformatted text preview: Brad Hill ELEC 7250 Logic Simulator 4/25/2006 4/25/2006 ELEC7250: Hill 1 Simulation Table Table created Table Gate Name Fan-in and Fan-out Input and Output Array Signal Array Holds Signal Value during simulation Set to 0 before each vector is applied 4/25/2006 4/25/2006 ELEC7250: Hill 2 Result Tables Primary Input and Primary Arrays Primary Contains value of each Input Vectors and Expected Output Contains Vectors Vectors Simulated Circuit Table Contains Input Vectors and Actual Output Vectors Simulation Table Gate Name Fan-in Fan-out These Tables are Used to Determine if there is and These error with specific input vectors error 4/25/2006 4/25/2006 ELEC7250: Hill 3 Diagnosis Back Track Incorrect Primary Outputs Trace path to gate that produced Output Suspected Gates and Signal List are Suspected formed formed Primary Output is First Suspected Signal The Gate that it originated from is the First The Suspected Gate Suspected 4/25/2006 4/25/2006 ELEC7250: Hill 4 Diagnosis Each Signal in the Suspected Signal List Each is traced to the gate it came from is Gates is added to Suspected Gate List The Gates Fan-in is used to gather more The signals for Suspected Signal List signals Removing Primary Inputs if any Keep Gate and Signal Lists for every Keep incorrect output incorrect 4/25/2006 4/25/2006 ELEC7250: Hill 5 Diagnosis It is likely that an Error in one gate will It cause many invalid outputs cause Each invalid output has its own Suspect list The different lists can be compared with The each other to find which Suspect Gate occurs the most occurs This Can Aid in Trying to Narrow the This Faulty Gate Down Faulty 4/25/2006 4/25/2006 ELEC7250: Hill 6 Complexity Depends on Complexity of Circuit Number of Fan-outs of Gates Number of Outputs Number of Gates Number Depth of Circuit Increase in Any of these will result in an Increase increase in execution time increase 4/25/2006 4/25/2006 ELEC7250: Hill 7 Conclusion Work well with Errors in Gates that are Work reflected in many Outputs reflected Work well with Errors in Gates that are Work reflected in different Outputs given different Inputs Inputs If there are not many Primary Outputs or Fanouts Will only provide Possible Paths the Faulty Gate is Will in in May take considerable execution time with May increasing numbers of Gates and Fan-outs increasing 4/25/2006 4/25/2006 ELEC7250: Hill 8 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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