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# lec9a - Lecture 9alt Combinational ATPG(A Shortened version...

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Copyright 2001, Agrawa VLSI Test: Lecture 9alt 1 Lecture 9alt Combinational ATPG (A Shortened version of Original Lectures 9-12) ATPG problem Algorithms Multi-valued algebra D-algorithm Podem ATPG system Summary Exercise

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Copyright 2001, Agrawa VLSI Test: Lecture 9alt 2 ATPG Problem ATPG: Automatic test pattern generation Given A circuit (usually at gate-level) A fault model (usually stuck-at type) Find A set of input vectors to detect all modeled faults. Core problem: Find a test vector for a given fault. Combine the “core solution” with a fault simulator into an ATPG system.
Copyright 2001, Agrawa VLSI Test: Lecture 9alt 3 What is a Test? X 1 0 0 1 0 1 X X Stuck-at-0 fault 1/0 Fault activation Path sensitization Primary inputs (PI) Primary outputs (PO) Combinational circuit 1/0 Fault effect

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Copyright 2001, Agrawa VLSI Test: Lecture 9alt 4 ATPG is a Search Problem Search the input vector space for a test: Initialize all signals to unknown (X) state – complete vector space is the playing field Activate the given fault and sensitize a path to a PO – narrow down to one or more tests X X X sa1 Circuit Vector Space X 0 1 sa1 Circuit Vector Space 0/1 001 101
Copyright 2001, Agrawa VLSI Test: Lecture 9alt 5 Need to Deal With Two Copies of the Circuit X 0 1 Good circuit 0 X 0 1 sa1 Faulty circuit 1 X 0 1 sa1 Circuit 0/1 Alternatively, use a multi-valued algebra of signal values for both good and faulty circuits. Same input Different outputs X X X

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Copyright 2001, Agrawa VLSI Test: Lecture 9alt 6 Multiple-Valued Algebras Symbol D D 0 1 X G0 G1 F0 F1 Alternative Representation 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Faulty Circuit 0 1 0 1 X X X 0 1 Fault-free circuit 1 0 0 1 X 0 1 X X Roth’s Algebra Muth’s Additions
Copyright 2001, Agrawa VLSI Test: Lecture 9alt 7 Function of NAND Gate c Input a 0 1 X D 0 1 1 1 1 1 1 1 0 X D X 1 X X X X D 1 X 1 1 D X 1 D D D D D D a b c D 1/0 0/1 D 1 Input b

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Copyright 2001, Agrawa VLSI Test: Lecture 9alt 8 D-Algorithm (Roth et al ., 1967, D-alg II) Use D-algebra Activate fault Place a D or D at fault site Do justification, forward implication and consistency check for all signals Repeatedly propagate D-chain toward POs through a gate Do justification, forward implication and consistency check for all signals Backtrack if A conflict occurs, or D-frontier becomes a null set Stop when D or D at a PO, i.e., test found, or If search exhausted without a test, then no test possible
Copyright 2001, Agrawa VLSI Test: Lecture 9alt 9 Definitions Justification: Changing inputs of a gate if the present input values do not justify the output value. Forward implication: Determination of the gate output value, which is X, according to the input values. Consistency check: Verifying that the gate output is justifiable from the values of inputs, which may have changed since the output was determined.

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