lec10 - f sa0 is masked when fault q sa1 is also present....

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Copyright 2001, Agrawa VLSI Test: Lecture 10 1 Lecture 10 Combinational ATPG and Logic Redundancy Redundancy identification Redundancy removal
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Copyright 2001, Agrawa VLSI Test: Lecture 10 2 Irredundant Hardware and Test Patterns Combinational ATPG cannot always find redundant (unnecessary) hardware Fault Test a sa1, b sa0 A = 1 a sa0, b sa1 A = 0 Therefore, these faults are not redundant
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Copyright 2001, Agrawa VLSI Test: Lecture 10 3 Redundant Hardware and Simplification
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Copyright 2001, Agrawa VLSI Test: Lecture 10 4 Redundant Fault q sa1
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Copyright 2001, Agrawa VLSI Test: Lecture 10 5 Multiple Fault Masking Single fault f sa0 is tested by input vector 110.
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Copyright 2001, Agrawa VLSI Test: Lecture 10 6 Multiple Fault Masking
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Unformatted text preview: f sa0 is masked when fault q sa1 is also present. Copyright 2001, Agrawa VLSI Test: Lecture 10 7 Intentional Redundant Implicant BC Elimination of hazards in circuit output Copyright 2001, Agrawa VLSI Test: Lecture 10 8 Fault Cone and D-frontier Fault Cone Set of hardware affected by fault D-frontier Set of gates closest to POs with fault effect(s) at input(s) Fault Cone D-frontier Copyright 2001, Agrawa VLSI Test: Lecture 10 9 Algorithm 7.1 (p. 171) Redundancy Removal Repeat until there are no redundant faults: { Use ATPG to find all redundant faults; Remove all redundant faults with non- overlapping fault cone areas; }...
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lec10 - f sa0 is masked when fault q sa1 is also present....

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