# lec13 - Lecture 13 Sequential Circuit ATPG Time-Frame...

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Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 1 Lecture 13 Sequential Circuit ATPG Time-Frame Expansion (Lecture 12alt in the Alternative Sequence) Problem of sequential circuit ATPG Time-frame expansion Nine-valued logic ATPG implementation and drivability Complexity of ATPG Cycle-free and cyclic circuits Asynchronous circuits Summary and Exercise

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Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 2 Sequential Circuits A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods
Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 3 Example: A Serial Adder FF A n B n C n C n+1 S n s-a-0 1 1 1 1 1 X X X D D Combinational logic

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Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 4 Time-Frame Expansion A n B n FF C n C n+1 1 X X S n s-a-0 1 1 1 1 D D Combinational logic S n-1 s-a-0 1 1 1 1 X D D Combinational logic C n-1 1 1 D D X A n-1 B n-1 Time-frame -1 Time-frame 0
Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 5 Concept of Time-Frames If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Comb. block Fault Time- frame 0 Time- frame -1 Time- Frame - n +1 Unknown or given Init. state Vector 0 Vector – 1 Vector – n +1 PO 0 PO – 1 PO – n +1 State variables Next state

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Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 6 Example for Logic Systems FF2 FF1 A B s-a-1
Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 7 Five-Valued Logic (Roth) 0,1, D , D , X A B X X X 0 s-a-1 D A B X X X 0 s-a-1 D FF1 FF1 FF2 FF2 D D Time-frame -1 Time-frame 0

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Copyright 2001, Agrawa VLSI Test: Lecture 13/12alt 8 Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/ X, 0/ X , X/ 0, X/ 1, X A B X X X 0 s-a-1 0/1 A B 0/ X 0/ X 0/1 X s-a-1 X /1 FF1 FF1 FF2 FF2 0/1 X /1 Time-frame -1 Time-frame 0
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## This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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lec13 - Lecture 13 Sequential Circuit ATPG Time-Frame...

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