lec14a - Lecture 14alt Memory Test(Alternative for Lecture...

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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 1 Memory organization Memory test complexity Faults and fault models MATS+ march test Address Decoder faults Summary References Lecture 14alt Lecture 14alt Memory Test Memory Test (Alternative for Lecture 15) (Alternative for Lecture 15)
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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 2 RAM Organization RAM Organization
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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 3 Test Time in Seconds Test Time in Seconds (Memory Cycle Time 60ns) (Memory Cycle Time 60ns) n bits 1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb 2 Gb n 0.06 0.25 1.01 4.03 16.11 64.43 128.9 n × log 2 n 1.26 5.54 24.16 104.7 451.0 1932.8 3994.4 n 3/2 64.5 515.4 1.2 hr 9.2 hr 73.3 hr 586.4 hr 1658.6 hr n 2 18.3 hr 293.2 hr 4691.3 hr 75060.0 hr 1200959.9 hr 19215358.4 hr 76861433.7 hr Size Number of Test Algorithm Operations
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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 4 SRAM Fault Modeling SRAM Fault Modeling Examples Examples SA0 AF+SAF SAF SCF <0;0> SCF <1;1> SA0 SA0 TF <↑/1> TF <↓/0>
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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 5 DRAM Fault Modeling DRAM Fault Modeling AND Bridging Fault (ABF) SA1+SCF SA1 ABF SCF SA0 ABF
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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 6 SRAM Only Fault Models SRAM Only Fault Models Faults found only in SRAM Open-circuited pull-up device Excessive bit line coupling capacitance Model DRF CF
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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 7 DRAM Only Fault Models DRAM Only Fault Models Faults only in DRAM Data retention fault (sleeping sickness) Refresh line stuck-at fault Bit-line voltage imbalance fault Coupling between word and bit line Single-ended bit-line voltage shift Precharge and decoder clock overlap Model DRF SAF PSF CF PSF AF
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Copyright 2005, Agrawa VLSI Test: Lecture 14alt 8 Reduced Functional Faults Reduced Functional Faults SAF TF CF NPSF Fault Stuck-at fault Transition fault Coupling fault Neighborhood Pattern Sensitive fault
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lec14a - Lecture 14alt Memory Test(Alternative for Lecture...

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