lec18a - Lecture 18alt IDDQ Testing (Alternative for...

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Copyright 2005, Agrawa VLSI Test: Lecture 18alt 1 Lecture 18alt I DDQ Testing (Alternative for Lectures 21 and 22) Definition Faults detected by I DDQ tests Weak fault Leakage fault Sematech and other studies ΔI DDQ testing Built-in current (BIC) sensor Summary
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Copyright 2005, Agrawa VLSI Test: Lecture 18alt 2 Basic Principle of I DDQ Testing Measure I DDQ current through V ss bus
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Copyright 2005, Agrawa VLSI Test: Lecture 18alt 3 NAND Open Circuit Defect – Floating gate
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Copyright 2005, Agrawa VLSI Test: Lecture 18alt 4 Floating Gate Defects Small break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunneling Delay fault and I DDQ fault Large open results in stuck-at fault – not detectable by I DDQ test If V tn < V fn < V DD – | V tp | then detectable by I DDQ test
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Copyright 2005, Agrawa VLSI Test: Lecture 18alt 5 Delay Faults Many random CMOS defects cause a timing delay fault, not catastrophic failure Some delay faults detected by I DDQ test – late switching of logic gates keeps I DDQ elevated Delay faults not detected by I DDQ test Resistive via fault in interconnect Increased transistor threshold voltage fault
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Copyright 2005, Agrawa VLSI Test: Lecture 18alt 6 Weak Faults n FET passes logic 1 as 5 V – V tn p FET passes logic 0 as 0 V + | V tp | Weak fault – one device in C-switch does not turn on Causes logic value degradation in C-switch
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Copyright 2005, Agrawa VLSI Test: Lecture 18alt 7 Weak Fault Detection Fault not detected unless I3 = 1
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lec18a - Lecture 18alt IDDQ Testing (Alternative for...

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