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lec20 - Lecture 20 Delay Test(Lecture 17alt in the...

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Copyright 2001, Agrawa VLSI Test: Lecture 20/17alt 1 Lecture 20 Delay Test (Lecture 17alt in the Alternative Sequence) Delay test definition Circuit delays and event propagation Path-delay tests Non-robust test Robust test Five-valued logic and test generation Path-delay fault (PDF) and other fault models Test application methods Combinational, enhanced-scan and normal-scan Variable-clock and rated-clock methods At-speed test Timing design and delay test Summary
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Copyright 2001, Agrawa VLSI Test: Lecture 20/17alt 2 Delay Test Definition A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. Delay test problem for asynchronous circuits is complex and not well understood.
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Copyright 2001, Agrawa VLSI Test: Lecture 20/17alt 3 Digital Circuit Timing Inputs Outputs time Transient region Clock period Comb. logic Output Observation instant Input Signal changes Synchronized With clock
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Copyright 2001, Agrawa VLSI Test: Lecture 20/17alt 4 Circuit Delays Switching or inertial delay is the interval between input change and output change of a gate: Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. Also depends on input rise or fall times and states of other inputs (second-order effects). Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. Propagation or interconnect delay is the time a transition takes to travel between gates: Depends on transmission line effects (distributed R , L , C parameters, length and loading) of routing paths. Approximation: modeled as lumped delays for gate inputs. See Section 5.3.5 for timing models.
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Copyright 2001, Agrawa VLSI Test: Lecture 20/17alt 5 Event Propagation Delays 2 4 6 1 1 3 5 3 1 0 0 0 2 2 Path P1 P2 P3 Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew
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Copyright 2001, Agrawa VLSI Test: Lecture 20/17alt 6 Circuit Outputs Each path can potentially produce one signal transition at the output. The location of an output transition in time is determined by the delay of the path. Initial value Initial value Final value Final value Clock period Fast transitions Slow transitions time
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Copyright 2001, Agrawa VLSI Test: Lecture 20/17alt 7 Singly-Testable Paths (Non-Robust Test) The delay of a target path is tested if the test propagates a transition via path to a path destination. Delay test is a combinational vector-pair, V1,V2, that: Produces a transition at path input. Produces static sensitization -- All off-path inputs assume non-controlling states in V2.
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