lec20a - Lecture 20alt DFT: Partial, Random-Access &...

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Copyright 2005, Agrawa VLSI Test: Lecture 20alt 1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan Definition Partial-scan architecture Historical background Cyclic and acyclic structures Partial-scan by cycle-breaking S-graph and MFVS problem Test generation and test statistics Partial vs. full scan Partial-scan flip-flop Random-access scan (RAS) Scan-hold flip-flop (SHFF) Boundary scan IEEE 1149.1 standard Summary
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Copyright 2005, Agrawa VLSI Test: Lecture 20alt 2 Partial-Scan Definition A subset of flip-flops is scanned. Objectives: Minimize area overhead and scan sequence length, yet achieve required fault coverage Exclude selected flip-flops from scan: Improve performance Allow limited scan design rule violations Allow automation: In scan flip-flop selection In test generation Shorter scan sequences
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Copyright 2005, Agrawa VLSI Test: Lecture 20alt 3 Partial-Scan Architecture FF FF SFF SFF Combinational circuit PI PO CK1 CK2 SCANOUT SCANIN TC
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Copyright 2005, Agrawa VLSI Test: Lecture 20alt 4 History of Partial-Scan Scan flip-flop selection from testability measures, Trischler et al ., ITC-80; not too successful. Use of combinational ATPG: Agrawal et al Functional vectors for initial fault coverage Scan flip-flops selected by ATPG Gupta et al ., IEEETC, Apr. 90 Balanced structure Sometimes requires high scan percentage Use of sequential ATPG: Cheng and Agrawal, IEEETC, Apr. 90; Kunzmann and Wunderlich, JETTA, May 90 Create cycle-free structure for efficient ATPG
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Copyright 2005, Agrawa VLSI Test: Lecture 20alt 5 Difficulties in Seq. ATPG Poor initializability. Poor controllability/observability of state variables. Gate count, number of flip-flops, and sequential depth do not explain the problem. Cycles are mainly responsible for complexity. An ATPG experiment: Circuit Number of Number of Sequential ATPG Fault gates flip-flops depth CPU s coverage TLC 355 21 14* 1,247 89.01% Chip A 1,112 39 14 269 98.80% * Maximum number of flip-flops on a PI to PO path
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Copyright 2005, Agrawa VLSI Test: Lecture 20alt 6 Benchmark Circuits Circuit PI PO FF Gates
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lec20a - Lecture 20alt DFT: Partial, Random-Access &...

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