# lec21a - Lecture 21alt BIST Built-In Self-Test(Alternative...

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Copyright 2005, Agrawa VLSI Test: Lecture 21alt 1 Lecture 21alt BIST -- Built-In Self-Test (Alternative to Lectures 25, 26 and 27) Definition of BIST Pattern generator LFSR Response analyzer MISR Aliasing probability BIST architectures Test per scan Test per clock Circular self-test Memory BIST Summary

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Copyright 2005, Agrawa VLSI Test: Lecture 21alt 2 Define Built-In Self-Test Implement the function of automatic test equipment (ATE) on circuit under test (CUT). Hardware added to CUT: Pattern generation (PG) Response analysis (RA) Test controller CUT Stored Test Patterns Stored responses Pin Electronics Comparator hardware Test control HW/SW ATE PG RA CUT Go/No-go signature Test control logic CK BIST Enable
Copyright 2005, Agrawa VLSI Test: Lecture 21alt 3 Pattern Generator (PG) RAM or ROM with stored deterministic patterns Counter Pseudorandom pattern generator Feedback shift register Cellular automata

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Copyright 2005, Agrawa VLSI Test: Lecture 21alt 4 Pseudorandom Integers 0 5 1 6 2 4 Start +3 Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2 . . . 0 1 6 2 4 Start +2 Sequence: 2, 4, 6, 0, 2 . . . X k = X k-1 + 3 ( modulo 8) X k = X k-1 + 2 ( modulo 8) Maximum length sequence: 3 and 8 are relative primes.
Copyright 2005, Agrawa VLSI Test: Lecture 21alt 5 Pseudo-Random Pattern Generation Standard Linear Feedback Shift Register (LFSR) Produces patterns algorithmically – repeatable Has most of desirable random # properties May not cover all 2 n input combinations Long sequences needed for good fault coverage either h i = 0, i.e., XOR is deleted or h i = X i Initial state (seed): X 0 , X 1 , . . . , X n- 1 must not be 0, 0, . . . , 0

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Copyright 2005, Agrawa VLSI Test: Lecture 21alt 6 Matrix Equation for Standard LFSR X 0 ( t + 1) X 1 ( t + 1) .
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lec21a - Lecture 21alt BIST Built-In Self-Test(Alternative...

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