lec23 - Lecture 23 Design for Testability (DFT): FullScan...

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Copyright 2001, Agrawa VLSI Test: Lecture 23/19alt 1 Lecture 23 Design for Testability (DFT): Full- Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary
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Copyright 2001, Agrawa VLSI Test: Lecture 23/19alt 2 Definition Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan DFT method for mixed-signal circuits: Analog test bus
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Copyright 2001, Agrawa VLSI Test: Lecture 23/19alt 3 Ad-Hoc DFT Methods Good design practices learnt through experience are used as guidelines: Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. Consider ATE requirements (tristates, etc.) Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary.
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VLSI Test: Lecture 23/19alt 4 Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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lec23 - Lecture 23 Design for Testability (DFT): FullScan...

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