Milton - testvector vales Simulate all PIs Simulate ALL...

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VLSI Testing Term Project Presentation Daniel Milton
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Project Accomplishments (so far) Each student is challenged to create own logic simulator for BENCH format and include an extension for hierarchy.
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UML Class Diagram
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Program Implementation Used Java 1.5 update 6 SDK jGRASP – IDE Approx 2000 lines of code.
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Simulation Algorithm Vector generation automatically generated according to Primary Inputs Each sim_node contains code for simulating every type of gate Initialize Pis to
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Unformatted text preview: testvector vales Simulate all PIs Simulate ALL outputs of PIs Get new testvector if no gates left to simulate Performance Results 170 250 470 951 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 Test Vectors Time (ms) 4- Bit Adder Test Data ISCA85 Performance Results 20 40 60 80 100 120 140 160 500 1000 1500 2000 2500 3000 # of Gates Minutes AMD Athlon (Thunderbird) 1.2 GHz , 384 MB RAM, Windows XP Home SP2 Questions?...
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Milton - testvector vales Simulate all PIs Simulate ALL...

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