Sheth - ELEC 7250 VLSI Testing Project Report Submitted By:...

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ELEC 7250 VLSI Testing Project Report Submitted By: Khushboo Sheth
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Contents 1. Preface…………………………………………3 2. Project Part 1………………………………….4 3. Project Part 2…………………………………21 4. Project Part-3…………………………………32 5. Project Part-4…………………………………51 6. Results ……………………………………….58 7. Conclusion and References………………. .59 2
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1. Preface Today’s world has been revolutionized by the rapid advancement of very large scale integration (VLSI) integrated circuit (IC) engineering. As the IC process technology becomes more complex and minimum feature size approaches nanometer range, manufacturing quality and yield are becoming more sensitive to physical defects. These defects are usually caused by mask contamination, process variation in fabrication, and spurious material Hence, mass production of digital systems, which has led to the enormous creation of wealth, relies critically on high-quality testing tools and techniques. The more commercially successful the design is, the more emphasis is placed on the quality of tests. This course teaches the exponential nature of the test problem, fault models, test generation algorithms, test generation for sequential circuits, fault simulation, testability measures, fault coverage, yield and defect levels, design-for-testability approaches, scan and boundary scan, IDDQ testing, mixed signal testing. After taking this course the fundamentals of the VLSI Testing, which I was not familiar to, became very clear after taking the course. The course seemed difficult initially but then gradually, as it was well taught, helped me gaining knowledge about the subject. I thank Dr. Vishwani Agrawal for helping me understand the subject well and for solving my difficulties. 3
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2. Project Part 1 Problem statement : Write a compiler for the hierarchical format which has two options to offer: Default option Generates a flat netlist Generates a simulation table for the flat netlist Hierarchical option Generate simulation tables for all subnetworks in the hierarchical netlist Simulation Table: Contains a gate record for each gate Gate name Gate type Fanin list Fanout list Other attributes Delays faults Algorithm used : 1. The user is asked for the circuit to become compiled and one of the two option given by the compiler 2. For the Hierarchical option the extension-h is given after the name of the file to be compiled and then the Hierarchical netlist of the circuit is read line by line and saved in the HierSim file and given to the user 3. For the Default option each of the hierarchical block is stored as an element in a block array then as the netlist is read the blocks are flattened and stored in an Object file which contains the flat netlist 4. This flat netlist is then read line by line and the flat simulation table is then created by the compiler and given to the user Language used to implement this algorithm: C Software used : TurboC-version 3 4
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Sheth - ELEC 7250 VLSI Testing Project Report Submitted By:...

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