Sheth - ELEC 7250 Term Project Presentation Khushboo Sheth...

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ELEC 7250 Term Project Presentation Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL
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Problem 1 Problem statement: Develop a compiler for the hierarchical format with 2 options for the user : Default option and Hierarchical option Algorithm used: User is asked for the circuit and the option Hierarchical Option: Hierarchical file read line by line and HierSim file having the Hierarchical simulation table is given to the user. Default Option: The different Hierarchical blocks are stored as an element in the block array and as the hierarchical netlist is read the blocks are flattened and stored in the Object file having the flat netlist. This Object file is then read to create the Flat simulation table in FlatSim file.
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Problem 2 Problem Statement: Develop a logic Simulator for combinational circuits consisting of zero-delay Boolean gates with hierarchical bench format netlist input and fully specified input vectors and expected responses. Algorithm used:
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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Sheth - ELEC 7250 Term Project Presentation Khushboo Sheth...

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