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# Wang - Final Project Report ELEC7250 Spring 2006 Instructor...

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Final Project Report ELEC7250 Spring 2006 Instructor: Professor Vishwani D. Agrawal Fan Wang Dept. of Electrical & Computer Engineering Auburn University April 29, 2006 1

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............................................................................................................................................ 2 1 Introduction ..................................................................................................................... 2 2 Project Objectives ............................................................................................................ 2 3 Project Process ................................................................................................................. 2 3.1 Circuit Description ............................................................................................................. 2 3.2 Compiler Design ................................................................................................................. 3 3.3 Logic Simulator Design ...................................................................................................... 4 3.4 Diagnose the design error .................................................................................................. 5 5 Conclusion ....................................................................................................................... 7 6 References ........................................................................................................................ 7 1 Introduction Currently, the CAD tools are very important for VLSI design because they handle the complexity and optimize the tradeoffs. The logic simulator is one of basic part to simulate the functionality of a circuit based on specific input. The complexity of logic simulator in sequential circuit is obvious. There are many research papers on this part in 1990s. Also, the compiler design in VLSI is a complex issue. Competition in the market is a driving force for CAD designer to make their tools much more convenient and effectively used by the users. 2 Project Objectives This VLSI testing final project aimed at writing a program to analyze the circuit description; writing a compiler to flatten hierarchical bench format circuit and generate simulation table; use specific algorithm to design a logic simulator for combinational circuit and try to diagnose the design error. 3 Project Process 3.1 Circuit Description Develop a hierarchical bench format for circuit description. Bench is a circuit description language used to describe the ISCAS85 and other benchmark circuits. Bellowing is the bench format for one bit full adder: #FA , 1- bit full adder #3 inputs 2
#2 outputs #0 inverters #5 gates INPUT(ci) INPUT(ai) INPUT(bi) OUTPUT(sumi) OUTPUT(Ci +1 ) 1=XOR(bi, ai) 2=AND(ai, bi) 3=AND(ci, 1) Sumi=XOR(1, ci) C i+1 =OR(3, 2) End Bench format: 1. # :followed by the overall circuit description 2. INPUT and OUTPUT define the inputs and outputs pins. 3. XOR, AND, XOR est. are the primitive gates , 1=XOR(bi, ai) equals 1=(bi and ai) and bi is the first input, ai is the second input of the and gate. 3.2 Compiler Design The compiler has two functions: 1. for hierarchical bench format, the compiler can flatten it. 2. For a flattened bench format, the compiler can generate simulation table. For convenience, the implementation of this part is by Matlab because Matlab has imbedded function to read the netlist file

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