Wang - Final Project Report ELEC7250 Spring 2006...

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Final Project Report ELEC7250 Spring 2006 Instructor: Professor Vishwani D. Agrawal Fan Wang Dept. of Electrical & Computer Engineering Auburn University April 29, 2006 1
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............................................................................................................................................ 2 1 Introduction ..................................................................................................................... 2 2 Project Objectives ............................................................................................................ 2 3 Project Process ................................................................................................................. 2 3.1 Circuit Description ............................................................................................................. 2 3.2 Compiler Design ................................................................................................................. 3 3.3 Logic Simulator Design ...................................................................................................... 4 3.4 Diagnose the design error .................................................................................................. 5 5 Conclusion ....................................................................................................................... 7 6 References ........................................................................................................................ 7 1 Introduction Currently, the CAD tools are very important for VLSI design because they handle the complexity and optimize the tradeoffs. The logic simulator is one of basic part to simulate the functionality of a circuit based on specific input. The complexity of logic simulator in sequential circuit is obvious. There are many research papers on this part in 1990s. Also, the compiler design in VLSI is a complex issue. Competition in the market is a driving force for CAD designer to make their tools much more convenient and effectively used by the users. 2 Project Objectives This VLSI testing final project aimed at writing a program to analyze the circuit description; writing a compiler to flatten hierarchical bench format circuit and generate simulation table; use specific algorithm to design a logic simulator for combinational circuit and try to diagnose the design error. 3 Project Process
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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Wang - Final Project Report ELEC7250 Spring 2006...

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