# White - ELEC7250 VLSI Testing Final Project Andrew White...

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Unformatted text preview: ELEC7250 VLSI Testing: Final Project Andrew White Andrew 4/27/2006 4/27/2006 ELEC7250: White 1 Overview Problem Description Plan Results Demonstration 4/27/2006 4/27/2006 ELEC7250: White 2 Plan Compiler – Hierarchical bench formats are flattened Logic Simulator – Used simulation table and test vectors – Two states (1,0) 4/27/2006 4/27/2006 ELEC7250: White 3 Plan Algorithm – Input vector is propogated through to the Input output output – Traverse through the gates in levels 4/27/2006 4/27/2006 ELEC7250: White 4 Results CPU Time vs. Number of Vectors 30 CPU Time (s) 25 20 15 10 5 0 10 210 410 610 810 1010 Vectors 4/27/2006 4/27/2006 ELEC7250: White 5 Results CPU Time vs. Number of Gates 10000 Time (s) 1000 100 Sequential 10 1 6 506 1006 1506 2006 2506 0.1 Gates 4/27/2006 4/27/2006 ELEC7250: White 6 Plan Due to long logic simulations – Parallelize the problem Parallel Approach – Same algorithm as the sequential approach – Main node broadcasts the simulation table to all other Main nodes nodes – Main node reads in test vector file and evenly distributes Main vectors to all other nodes vectors – Each node computes vector values and reports the Each results to the main node results 4/27/2006 4/27/2006 ELEC7250: White 7 Results CPU Time vs. Number of Gates 14000 12000 Time (s) 10000 8000 Parallel (2 PE's) Sequential 6000 4000 2000 0 6 162 1002 2416 Gates 4/27/2006 4/27/2006 ELEC7250: White 8 Fault Diagnosis Find faulty vector Find faulty outputs Algorithm complexity 4/27/2006 4/27/2006 ELEC7250: White 9 Demonstration C17 Circuit 4/27/2006 4/27/2006 ELEC7250: White 10 Conclusion Questions/Comments? 4/27/2006 4/27/2006 ELEC7250: White 11 ...
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