White_BoundaryScan

White_BoundaryScan - Andrew White Boundary Scan Standard...

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Andrew White Boundary Scan Standard Andrew White Abstract – Boundary scan, also known as IEEE standard 1149.1, is described by the Test Technology Standards Committee of the IEEE Computer Society as “circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards” [1]. This standard has become widely used in today’s printed circuit boards (PCBs) to reduce testing time along with cost. In this paper the IEEE 1149.1 standard’s history, reasoning, and implementations will be discussed. I. I NTRODUCTION I n the mid 1980’s the Joint European Test Action Group (JETAG) was formed in Europe and began developing the Boundary Scan Standard. By 1986 JETAG included not only Europe but also North America and was thus renamed JTAG. After a series of proposals for a standardized form of boundary scan, the IEEE Society finally approved one of them in 1988. Due to the acceptance of the standard from JTAG, JTAG became the core of the group that founded the standard. The initial approval of the standard came in February of 1990 followed by almost immediate supplements. As the standard claims, it defines test logic that can be included into the integrated circuit (IC) to provide easy testing of the interconnections along with the IC itself. The test logic consists of boundary-scan registers, Test Access Port (TAP), and other building blocks. II. P URPOSE It was in the 1970’s when in-circuit testing (ICT) became known by testing the backs of PCBs with a board of pins. These testing boards covered in pins became known as a bed-of-nails tester. The reason for the name is simply the design of the test board itself because it is truly what it sounds like, a bed of nails. One of the reasons for this type of ICT was used was because of the way PCBs were actually manufactured. At that time, PCB’s were manufactured using a through-hole method in which all the ICs were manufactured using dual in-line (DIP) packages as depicted below in Figure 1. Figure 1. DIP. Since this type of packaging allowed the pins to actually go through the PCBs a connection to every chip could be made through the back of the board. Due to this characteristic a bed-of-nails tester could apply and read signals from any connection in the circuit. A lot has changed since the ICT method first began including, but no limited to, PCB manufacturing. One significant change that has made obsolete the bed-of-nails testers is surface-mount technology (SMT). SMT is the current method used for manufacturing PCB’s due to its low board real estate along with its added
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Andrew White pins. A depiction of an SMT component is shown below in Figure 2. Figure 2. Ball Grid Array showing SMT
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This note was uploaded on 09/16/2011 for the course ELEC 7250 taught by Professor Agrawal during the Summer '11 term at Auburn University.

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White_BoundaryScan - Andrew White Boundary Scan Standard...

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