lec4_high_level_power_analysis

lec4_high_level_power_analysis - High-level Power Analysis...

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Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 4 High-level Power Analysis
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2 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 4 Outline Background CMOS Power Consumption Basics Why Address Power Consumption Issues in High-Level Design High-Level Power Analysis RTL Power Estimation Fast Synthesis Analytical Approaches Characterization Accelerating RTL Power Estimation Power Emulation (Hardware Accelerated Power Estimation) Beyond RTL Power Estimation Power Estimation at the Cycle-accurate Behavior Level Architectural Power Estimation
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3 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 4 CMOS Power Consumption Basics What are the various components of CMOS power consumption?
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4 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 4 Levels of Design Abstraction (d) Transistor-level layout Logic Synthesis FSM reg_c0 reg_c1 reg_y1 reg_x reg_y != < - Controller input_y input_x out x = input_x; y = input_y; while (x != y) {     if (x < y) {        y  = y - x;     } else {        x  = x - y;     } } out = x; (a)Behavioral description Scheduling Binding ST_1:       x = input_x;       y = input_y;       goto ST_2; ST_2:       c0 = x!=y;       c1 = x<y;       y1 = y –x;       goto ST_3 (b) Cycle-accurate functional description (c) RTL description (d) Logic-level netlist Layou t
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5 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 4 Why Address Power at Higher Levels of Design Abstraction? System-level design Power models for system-level components System-level power analysis High-level synthesis, RTL optimizations Architecture-level power analysis Power models for macroblocks, control logic Logic synthesis Logic-level power analysis Power models for gates, cells, nets Transistor-level/ Layout synthesis Transistor-level power analysis Design flow with high-level power analysis System level Algorithm level Register-transfer level Logic level Layout level Transistor level Power reduction opportunities Power analysis iteration times 10-20X 2-5X 20 - 50% seconds - minutes minutes - hours hours - days Increasing power savings Decreasing design iteration times Benefits: Estimation Early feedback about power budget Faster / Fewer design iterations Benefits: Optimization Large power savings possible at  higher levels
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6 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 4 Outline Background CMOS Power Consumption Basics Why Address Power Consumption Issues in High-Level Design High-Level Power Analysis RTL Power Estimation Fast Synthesis Analytical Approaches Characterization Accelerating RTL Power Estimation Power Emulation (Hardware Accelerated Power Estimation) Beyond RTL Power Estimation Power Estimation at the Cycle-accurate Behavior Level Architectural Power Estimation
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7 Copyright Agarwal & Srivaths, 2007
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lec4_high_level_power_analysis - High-level Power Analysis...

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