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lec7_high_level_power_management

lec7_high_level_power_management - High-level Power...

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Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 7 High-level Power Reduction and Management
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2 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 7 Outline General Observations RTL Power Management Techniques Gated Clock Architecture Precomputation Guarded Evaluation Behavior-Level Power Reduction Techniques Performance Speedup Techniques Algebraic Transformations Common Case Computation Switched Capacitance Reduction Algebraic Transformations Power Supply Gating Basic Concept Isolation Cells Retention Flip-Flops
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3 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 7 General Observations Not all components need to be active all the time Energy-efficient computations achieved by selectively turning off (or reducing the performance of) system components when they are idle Issues: Controls to support power management Frequency control (clock gating) Voltage control (power shutdown) Identify when circuits (or parts) can be idle Location of controls Hardware Software (Hybrid)
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4 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 7 Outline General Observations RTL Power Management Techniques Gated Clock Architecture Precomputation Guarded Evaluation Behavior-Level Power Reduction Techniques Performance Speedup Techniques Algebraic Transformations Common Case Computation Switched Capacitance Reduction Algebraic Transformations Power Supply Gating Basic Concept Isolation Cells Retention Flip-Flops
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5 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 7 Gated Clock Architecture Block F a is controlled by primary inputs, state, and primary outputs Combinational Logic CLK STATE IN GCLK & L f a OUT Latch L takes care of filtering glitches L is transparent when clock is inactive
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6 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 7 Gated Clock Architecture : Redundant Clocking Detection Idea [Ohnishi97]: Redundant clockings activate registers unnecessarily Use application profiles to detect redundant clockings Difference in the numbers of incoming and outgoing data of a register Gated clock scheme designed using this information Redundant behaviors of a register Unused data latching: Data not transferred to a destination Unchanged data latching: Register re-stores data already present from source
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7 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 7 Redundant Clocking Detection # Unused data latching(X) or = 8 - 6 = 2 # Unchanged data latching(X) or = 8 - 5 = 3 # Redundant data holding(X) or = 10 – Identify the redundant behaviors for register X during the 10 clock cycle snapshot shown.
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