lec8_test_power - Copyright Agarwal & Srivaths,...

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Unformatted text preview: Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Test Power 2 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Outline Test Power Problem: Background and Basics Increasing Test Power Concerns Aspects of Test Power Dissipation DFT techniques targeting test power Power-aware ATPG Power Analysis Methodologies and Issues 3 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 4 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Testing Differs from Function: Functional Mode VLSI chip system System inputs System outputs Functional inputs Functional outputs Other chips 5 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Testing Differs from Function: Test Mode VLSI chip Test vectors: Pre-generated and stored in ATE DUT output for comparison with expected response stored in ATE Automatic Test Equipment (ATE): Control processor, vector memory, timing generators, power module, response comparator Power Clock Packaged or unpackaged device under test (DUT) 6 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Scan Testing Combinational logic Scan flip- flops Primary inputs Primary outputs Scan-in SI Scan-out SO Scan enable SE D Q DFF mux SE SD D Q SO 1 Scan flip-flop Sequential Circuit with Scan Scan Flip-Flop An example scan based test During response shift-out, next pattern can be concurrently shifted in. Shift-In Shift-Out Capture time 7 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Testing Differs from Function: Functional Inputs vs. Test Vectors Functional inputs: Functionally meaningful signals Generated by circuitry Restricted set of inputs May have been optimized to reduce logic activity and power Test vectors: Functionally irrelevant signals Generated by software to test faults Can be random or pseudorandom May be optimized to reduce test time; can have high logic activity May use testability logic for test application 8 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Terminology* Design-for-test (DFT): Modifications to the circuit for facilitating test. e.g. scan flip-flop insertion Automatic Test Pattern Generation (ATPG): Process of automatically generating test patterns that can be applied to the chip Pattern generation happens on the gate-level netlist of the circuit assuming a certain set of eventual defects/faults Fault Models: Abstraction of potential defects to ease the task of ATPG E.g., stuck-at faults, transition faults Compression: Technology for reduced test data volume/test application time. Compressed patterns are stored on the tester, while on-chip de-compression logic * See [Agarwal00] for more information on basics/ advanced concepts in testing 9 Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Outline Test Power Problem: Background and Basics...
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lec8_test_power - Copyright Agarwal & Srivaths,...

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