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Unformatted text preview: ELEC 7770: Advanced VLSI Design
Spring 2010
(Also, ELEC 7250 Class on March 11, 2010) Radio Frequency (RF) Testing
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10
Spring 2010, Mar 11 . . .
Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 References
References
1. S. Bhattacharya and A. Chatterjee, "RF Testing," Chapter 16, pages
S.
2.
3.
4.
5.
6. 745789, in System on Chip Test Archiitectures, edited by L.T. Wang,
tectures,
System
C. E. Stroud and N. A. Touba, Amsterdam: MorganKaufman, 2008.
C.
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for
M.
Digital, Memory & MixedSignal VLSI Circuits, Boston: Springer,
Digital,
Boston:
2000.
2000.
J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC,
J.
and SiP Devices, Boston: Artech House, 2007.
and
B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey:
B.
RF
Upper
Prentice Hall PTR, 1998.
Prentice
J. Rogers, C. Plett and F. Dai, Integrated Circuit Design for HighJ.
Integrated
Speed Frequency Synthesis, Boston: Artech House, 2006.
K. B. Schaub and J. Kelly, Production Testing of RF and SystemonK.
Production
achip Devices for Wireless Communications, Boston: Artech House,
Boston:
2004.
2004.
2 Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) An RF Communications System
An
Superheterodyne Transceiver
0°
VGA LNA Phase
Splitter LO Duplexer 90°
ADC LO DAC
0°
PA VGA Phase
Splitter LO 90° Digital Signal Processor (DSP) ADC DAC RF
Spring 2010, Mar 11 . . . IF
ELEC 7770: Advanced VLSI Design (Agrawal) BASEBAND
3 An Alternative RF Communications System
An
ZeroIF (ZIF) Transceiver
0°
Phase
Splitter LNA LO Duplexer 90°
ADC
DAC
0°
Phase
Splitter PA LO 90° Digital Signal Processor (DSP) ADC DAC RF
Spring 2010, Mar 11 . . . BASEBAND ELEC 7770: Advanced VLSI Design (Agrawal) 4 Components of an RF System
Components Radio frequency Duplexer
LNA: Low noise amplifier
PA: Power amplifier
RF mixer
Local oscillator
Filter Mixedsignal ADC: Analog to digital
ADC:
converter
converter DAC: Digital to analog
DAC:
converter
converter Digital Digital signal processor
Digital
(DSP)
(DSP) IIntermediate
ntermediate
frequency
frequency VGA: Variable gain
VGA:
amplifier
amplifier Modulator Demodulator Filter
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 5 LNA: Low Noise Amplifier
LNA: Amplifies received RF signal Typical characteristics: Noise figure
IP3
Gain
Input and output impedance
Reverse isolation
Stability factor 2dB
– 10dBm
15dB
50Ω
20dB
>1 Technologies: Bipolar CMOS Reference: Razavi, Chapter 6.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 6 PA: Power Amplifier
PA: Feeds RF signal to antenna for transmission Typical characteristics: Output power
Efficiency
IMD
Supply voltage
Gain
Output harmonics
Power control
Stability factor +20 to +30 dBm
30% to 60%
– 30dBc
3.8 to 5.8 V
20 to 30 dB
– 50 to – 70 dBc
Onoff or 1dB steps
>1 Technologies: GaAs SiGe Reference: Razavi, Chapter 9.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 7 Mixer or Frequency (Up/Down) Converter
Mixer Translates frequency by adding or subtracting
Translates local oscillator (LO) frequency
local
Typical characteristics: Noise figure
IP3
Gain
Input impedance
Port to port isolation 12dB
+5dBm
10dB
50Ω
1020dB Tecnologies: Bipolar MOS Reference: Razavi, Chapter 6.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 8 LO: Local Oscillator
LO: Provides signal to mixer for down conversion or
Provides upconversion.
upconversion.
Implementations: Tuned feedback amplifier Ring oscillator Phaselocked loop (PLL) Direct digital synthesizer (DDS) Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 9 SOC: SystemonaChip
SOC: All components of a system are implemented on
All the same VLSI chip.
the
Requires same technology (usually CMOS)
Requires
used for all components.
used
Components not implemented on presentday
Components
SOC:
SOC: Antenna Power amplifier (PA) Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 10 RF Tests
RF Basic tests Scattering parameters (Sparameters) Frequency and gain measurements Power measurements Power efficiency measurements Distortion measurements Noise measurements Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 11 Scattering Parameters (SParameters)
Scattering An RF function is a twoport device with Characteristic impedance (Z0): Z0 = 50Ω for wireless communications devices Z0 = 75Ω for cable TV devices Gain and frequency characteristics SParameters of an RF device S11 : input return loss or input reflection coefficient S22 : output return loss or output reflection coefficient S21 : gain or forward transmission coefficient S12 : isolation or reverse transmission coefficient
12 SParameters are complex numbers and can be
SParameters
expressed in decibels as 20 × log  Sij 
expressed Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 12 Active or Passive RF Device
Active
a1 a2 Port 1
(input) RF
Device Port 2
(output) b1 b2 Input return loss
Output return loss
Gain
Isolation
Spring 2010, Mar 11 . . . S11 = b1/a1
S22 = b2/a2
S21 = b2/a1
S12 = b1/a2 ELEC 7770: Advanced VLSI Design (Agrawal) 13 SParameter Measurement by Network Analyzer
SParameter
Directional couplers DUT
a1
Digitizer
b1
Directional couplers a2
Digitizer
b2
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 14 Application of SParameter: Input
Match
Match Example: In an Sparameter measurement
Example:
setup, rms value of input voltage is 0.1V and the
rms value of the reflected voltage wave is 0.02V.
Assume that the output of DUT is perfectly
matched. Then S11 determines the input match:
matched.
input S11 = 0.02/0.1 = 0.2, or 20 × log (0.2) = –14 dB. Suppose the required input match is –10 dB; this
Suppose
device passes the test.
device Similarly, S22 determines the output match.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 15 Gain (S21) and Gain Flatness
Gain An amplifier of a Bluetooth transmitter operates over a
An frequency band 2.4 – 2.5GHz. It is required to have a gain of
20dB and a gain flatness of 1dB.
20dB
Test: Under properly matched conditions, S21 is measured at
several frequencies in the range of operation:
several S21 = 15.31 at 2.400GHz S21 = 14.57 at 2.499GHz From the measurements: At 2.400GHz, Gain = 20×log 15.31 = 23.70 dB At 2.499GHz, Gain = 20×log 14.57 = 23.27 dB Result: Gain and gain flatness meet specification.
Result:
Measurements at more frequencies in the range may be
useful.
useful.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 16 Power Measurements
Power Receiver Minimum detectable RF power Maximum allowed input power Power levels of interfering tones Transmitter Maximum RF power output
Changes in RF power when automatic gain control is used
RF power distribution over a frequency band
Poweradded efficiency (PAE) Power unit: dBm, relative to 1mW Power in dBm = 10 × log (power in watts/0.001 watts) Example: 1 W is 10×log 1000 = 30 dBm What is 2 W in dBm?
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 17 Harmonic Measurements
Harmonic Multiples of the carrier frequency are called
Multiples harmonics.
harmonics.
Harmonics are generated due to nonlinearity in
Harmonics
semiconductor devices and clipping (saturation)
in amplifiers.
in
Harmonics may interfere with other signals and
Harmonics
must be measured to verify that a manufactured
device meets the specification.
device Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 18 PowerAdded Efficiency (PAE)
PowerAdded Definition: Poweradded efficiency of an RF amplifier is
Definition:
the ratio of RF power generated by the amplifier to the
DC power supplied:
DC
where PAE = ΔPRF / PDC
PAE
=
PRF(output) – PRF(input) ΔPRF
=
Vsupply × Isupply Pdc
supply Important for power amplifier (PA). 1 – PAE is a measure of heat generated in the amplifier,
PAE i.e., the battery power that is wasted.
i.e.,
In mobile phones PA consumes most of the power. A
In
low PAE reduces the usable time before battery
recharge.
recharge. Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 19 PAE Example
PAE Following measurements are obtained for an RF
Following power amplifier:
power RF Input power =
+2dBm RF output power =
+34dBm DC supply voltage =
3V DUT current
=
2.25A
PAE is calculated as follows:
= 0.001 × 102/10 = 0.0015W PRF(input)
= 0.001 × 1034/10 = 2.5118W PRF(output)
= 3× 2.25
= 6.75W Pdc PAE = (2.5118 – 0.00158)/6.75 = 0.373 or 37.2% Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 20 Distortion and Linearity
Distortion An unwanted change in the signal behavior is
An usually referred to as distortion.
distortion
The cause of distortion is nonlinearity of
The
semiconductor devices constructed with diodes
and transistors.
and
Linearity: Function f(x) = ax + b, although a straightline is not
Function referred to as a linear function.
referred
Definition: A linear function must satisfy: f(x + y) = f(x) + f(y), and f(ax) = a f(x), for all scalar constants a Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 21 Linear and Nonlinear Functions
Linear
f(x) f(x) slope = a
b b
x x f(x) = ax + b f(x) = ax2 + b
f(x) slope = a
x
f(x) = ax
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 22 Generalized Transfer Function
Generalized Transfer function of an electronic circuit is, in
Transfer general, a nonlinear function.
general,
Can be represented as a polynomial: vo = a0 + a1 vi + a2 vi2 + a3 vi3 + · · · · Constant term a0 is the dc component that in RF circuits is usually removed by a capacitor or highcircuits
pass filter.
For a linear circuit, a2 = a3 = · · · · = 0.
Electronic
vi Spring 2010, Mar 11 . . . circuit ELEC 7770: Advanced VLSI Design (Agrawal) vo 23 Effect of Nonlinearity on Frequency
Effect Consider a transfer function, vo = a0 + a1 vi + a2 vi2 + a3 vi3
Let vi = A cos ωt
Using the identities (ω = 2πf): cos2 ωt = (1 + cos 2ωt)/2 cos3 ωt = (3 cos ωt + cos 3ωt)/4
(3
We get, vo = a0 + a2A2/2 + (a1A + 3a3A3/4) cos ωt
/4) + (a2A2/2) cos 2ωt + (a3A3/4) cos
/4)
3ωt
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 24 Problem for Solution
Problem A diode characteristic is, I = Is ( eαV – 1) Where, V = V0 + vin, V0 is dc voltage and vin is small signal ac voltage. Is is saturation current and α is a constant that
voltage.
depends on temperature and design parameters of diode.
depends
Using the Taylor series expansion, express the diode current
Using
I as a polynomial in vin.
as
I 0 V – Is
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 25 Linear and Nonlinear Circuits and
Systems
Systems Linear devices: All frequencies in the output of a device are related to
All input by a proportionality, or weighting factor,
independent of power level.
independent No frequency will appear in the output, that was not
No
present in the input.
present
Nonlinear devices: A ttrue linear device is an idealization. Most electronic
rue
devices are nonlinear.
devices Nonlinearity in amplifier is undesirable and causes
Nonlinearity
distortion of signal.
distortion Nonlinearity in mixer or frequency converter is essential.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 26 Types of Distortion and Their Tests
Types Types of distortion: Harmonic distortion: singletone test Gain compression: singletone test Intermodulation distortion: twotone or multitone test Testing procedure: Output spectrum
Testing
measurement
measurement Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 27 Harmonic Distortion
Harmonic Harmonic distortion is the presence of multiples of a
Harmonic fundamental frequency of interest. N times the
fundamental frequency is called Nth harmonic.
Disadvantages: Waste of power in harmonics. Interference from harmonics.
Measurement: Singlefrequency input signal applied. Amplitudes of the fundamental and harmonic
Amplitudes
frequencies are analyzed to quantify distortion as:
frequencies Total harmonic distortion (THD) Signal, noise and distortion (SINAD) Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 28 Problem for Solution
Problem Show that for a nonlinear device with a single
Show
frequency input of amplitude A, the nth harmonic
the th
component in the output always contains a term
proportional to An. Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 29 Total Harmonic Distortion (THD)
Total THD is the total power contained in all harmonics of a
THD
signal expressed as percentage (or ratio) of the
fundamental signal power.
fundamental
THD(%) = [(P2 + P3 + · · · ) / Pfundamental ] × 100% Or THD(%) = [(V22 + V32 + · · · ) / V2fundamental ] × 100% Where P2, P3, . . . , are the power in watts of second, third, . . . ,
are harmonics, respectively, and Pfundamental is the fundamental signal
harmonics,
power,
power,
And V2, V3, . . . , are voltage amplitudes of second, third, . . . ,
are
harmonics, respectively, and Vfundamental is the fundamental signal
harmonics,
amplitude.
amplitude. Also, THD(dB) = 10 log THD(%) For an ideal distortionless signal, THD = 0% or – ∞ dB Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 30 THD Measurement
THD THD is specified typically for devices with RF
THD output.
output.
Separate power measurements are made for the
Separate
fundamental and each harmonic.
fundamental
THD is tested at specified power level because THD may be small at low power levels. Harmonics appear when the output power of an RF
Harmonics
device is raised.
device Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 31 Gain Compression
Gain The harmonics produced due to nonlinearity in an
The amplifier reduce the fundamental frequency power
output (and gain). This is known as gain
compression.
compression
As input power increases, so does nonlinearity
As
causing greater gain compression.
causing
A standard measure of Gain compression is “1dB
standard
compression point” power level P1dB, which can be
compression IInput referred for receiver, or
nput
for Output referred for transmitter
Output
for Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 32 Amplitude Amplitude Linear Operation: No Gain
Compression
Compression
time time f1 Spring 2010, Mar 11 . . . frequency Power (dBm) Power (dBm) LNA
or PA ELEC 7770: Advanced VLSI Design (Agrawal) f1 frequency 33 Amplitude Amplitude Cause of Gain Compression:
Clipping
Clipping
time time f1 Spring 2010, Mar 11 . . . frequency Power (dBm) Power (dBm) LNA
or PA ELEC 7770: Advanced VLSI Design (Agrawal) f1 f2 f3 frequency 34 Effect of Nonlinearity
Effect Assume a transfer function, vo = a0 + a1 vi + a2 vi2
+ a3 vi3 Let vi = A cos ωt Using the identities (ω = 2πf): cos2 ωt = (1 + cos 2ωt)/2 cos3 ωt = (3 cos ωt + cos 3ωt)/4
(3
We get,
= a0 + a2A2/2 + (a1A + 3a3A3/4) cos ωt vo
/4) + (a2A2/2) cos 2ωt + (a3A3/4) cos
/4)
3ωt Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 35 Gain Compression Analysis
Gain DC term is filtered out. For smallsignal input, A is small A2 and A3 terms are neglected vo = a1A cos ωt, smallsignal gain, G0 = a1
cos Gain at 1dB compression point, G1dB = G0 – 1 Input referred and output referred 1dB power:
P1dB(output) – P1dB(input) = G1dB = G0 – 1 Spring 2010, Mar 11 . . .
36 ELEC 7770: Advanced VLSI Design (Agrawal) 1 dB op
e = ga
in 1 dB
Compression
point Sl P1dB(output) Output power (dBm) 1dB Compression Point
1dB Linear region
(smallsignal)
P1dB(input)
Spring 2010, Mar 11 . . . Compression
region Input power (dBm) ELEC 7770: Advanced VLSI Design (Agrawal) 37 Testing for Gain Compression
Testing Apply a singletone input signal:
1. Measure the gain at a power level where DUT is
Measure
2.
3.
4. linear.
linear.
Extrapolate the linear behavior to higher power
Extrapolate
levels.
levels.
Increase input power in steps, measure the gain
Increase
and compare to extrapolated values.
and
Test is complete when the gain difference between
Test
steps 2 and 3 is 1dB.
steps Alternative test: After step 2, conduct a binary
Alternative
search for 1dB compression point.
search
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 38 Example: Gain Compression Test
Example: Smallsignal gain, G0 = 28dB
28dB IInputreferred 1dB compression point power
nputreferred
level,
level,
P1dB(input) = – 19 dBm
19 We compute: 1dB compression point Gain, G1dB = 28 – 1 = 27 dB Outputreferred 1dB compression point power level,
Outputreferred
P1dB(output)
1dB(output) P1dB(input) + G1dB =
Spring 2010, Mar 11 . . . = – 19 + 27 = 8 dBm ELEC 7770: Advanced VLSI Design (Agrawal) 39 Intermodulation Distortion
Intermodulation IIntermodulation distortion is relevant to devices that handle
ntermodulation multiple frequencies.
multiple
Consider an input signal with two frequencies ω1 and ω2:
Consider
vi = A cos ω1t + B cos ω2t
cos Nonlinearity in the device function is represented by
vo = a0 + a1 vi + a2 vi2 + a3 vi3, neglecting higher order terms
neglecting Therefore, device output is
vo = a0 + a1 (A cos ω1t + B cos ω2t)
cos DC and fundamental + a2 (A cos ω1t + B cos ω2t)2
cos 2nd order terms + a3 (A cos ω1t + B cos ω2t)3
cos 3rd order terms Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 40 Problems to Solve
Problems Derive the following:
vo = a0 + a1 (A cos ω1t + B cos ω2t)
cos
+ a2 [ A2 (1+cos 2ω1t)/2 + AB cos (ω1+ω2)t
)t
+ AB cos (ω1 – ω2)t + B2 (1+cos 2ω2t)/2 ]
AB
+ a3 (A cos ω1t + B cos ω2t)3
cos Hint: Use the identity: cos α cos β = [cos(α + β) + cos(α – β)] / 2
cos Simplify a3 (A cos ω1t + B cos ω2t)3
cos
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 41 TwoTone Distortion Products
TwoTone Order for distortion product mf1 ± nf2 is m + n
Nunber of distortion products
Order Harmonic Frequencies Intermod. Total Harmonic Intrmodulation 2 2 2 4 2f1 , 2f2 f1 + f2, f2 – f1 3 2 4 6 3f1 , 3f2 2f1 ± f2, 2f2 ± f1 4 2 6 8 4f1 , 4f2 2f1 ± 2f2, 2f2 – 2f1,
3f1 ± f2, 3f2 ± f1 5 2 8 10 5f1 , 5f2 3f1 ± 2f2, 3f2 ± 2f1,
4f1 ± f2, 4f2 ± f1 6 2 10 12 6f1 , 6f2 3f1 ± 3f2, 3f2 – 3f1, 5f1 ± f2,
5f2 ± f1, 4f1 ± 2f2, 4f2 ± 2f1 7 2 12 14 7f1 , 7f2 4f1 ± 3f2, 4f2 – 3f1, 5f1 ±
2f2, 5f2 ± 2f1, 6f1 ± f2, 6f2 ±
f1 N 2 2N – 2 2N Nf1 , Nf2 ..... Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 42 Problem to Solve
Problem
Write Distortion products tones 100MHz and 101MHz
Order Harmonics
(MHz) Intermodulation products (MHz) 2 200, 202 1, 201 3 300, 303 99, 102, 301, 302 4 400, 404 2, 199, 203, 401, 402, 403 5 500, 505 98, 103, 299, 304, 501, 503, 504 6 600, 606 3, 198, 204, 399, 400, 405, 601, 603, 604,
605 7 700, 707 97, 104, 298, 305, 499, 506, 701, 707,
703, 704, 705, 706 Intermodulation products close to input tones are shown in bold.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 43 f 1 f2
frequency Spring 2010, Mar 11 . . . f2 – f 1 DUT Amplitude Amplitude SecondOrder Intermodulation
Distortion
Distortion ELEC 7770: Advanced VLSI Design (Agrawal) f1 f2 2f 2f
1 frequency 2 44 Amplitude HigherOrder Intermodulation
Distortion
Distortion
DUT Thirdorder intermodulation
distortion products (IMD3)
2f2 – f1 Amplitude frequency 2f1 – f2 f1 f 2 f1 f2 2f 2f 3f1 3f2 frequency
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 45 Problem to Solve
Problem For A = B, i.e., for two input tones of equal
For
magnitudes, show that:
magnitudes, Output amplitude of each fundamental frequency, f1
or f2 , is
or 9
a1 A + — a3 A3 ≈
4 a1 A Output amplitude of each thirdorder intermodulation
Output
frequency, 2f1 – f2 or 2f2 – f1 , is
frequency, Spring 2010, Mar 11 . . . 3
— a3 A3
4 ELEC 7770: Advanced VLSI Design (Agrawal) 46 ThirdOrder Intercept Point (IP3)
ThirdOrder IIP3 is the power level of the fundamental for which the
P3 a1 IP3 = 3a3 IP33 / 4
IP3 = [4a1 /(3a3 )]1/2 Output output of each fundamental frequency equals the output
of the closest thirdorder intermodulation frequency.
of
IP3 is a figure of merit that quantifies the thirdorder
IP3
intermodulation distortion.
intermodulation
Assuming a1 >> 9a3 A2 /4, IP3 is given by a1 A 3a3 A3 / 4 IP3
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) A
47 Test for IP3
Test Select two test frequencies, f1 and f2, applied in equal
applied magnitude to the input of DUT.
magnitude
Increase input power P0 (dBm) until the thirdorder
products are well above the noise floor.
products
Measure output power P1 in dBm at any fundamental
frequency and P3 in dBm at a thirdorder intermodulation
frequency
frquency.
frquency.
Outputreferenced IP3: OIP3 =
P1 + (P1 – P3) / 2
OIP3 Inputreferenced IP3: IIP3
IIP3 = P0 + (P1 – P3) / 2 = OIP3 – G Because, Gain for fundamental frequency, G = P1 – P0
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 48 IP3 Graph
IP3
Output power (dBm) OIP3 P1 f1 or f2
20 log a1 A
slope = 1 2f1 – f2 or 2f2 – f1
20 log (3a3 A3 /4)
slope = 3 P3
(P1 – P3)/2
P0 IIP3 Input power = 20 log A dBm
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 49 Example: IP3 of an RF LNA
Example: Gain of LNA = 20 dB
RF signal frequencies: 2140.10MHz and 2140.30MHz
Secondorder intermodulation distortion: 400MHz; outside
Secondorder
operational band of LNA.
operational
Thirdorder intermodulation distortion: 2140.50MHz; within the
Thirdorder
operational band of LNA.
operational
Test: Input power, P0 = – 30 dBm, for each fundamental frequency
Output power, P1 = – 30 + 20 = – 10 dBm
Measured thirdorder intermodulation distortion power, P3 = – 84 dBm
OIP3 = – 10 + [( – 10 – ( – 84))] / 2 = + 27 dBm
IIP3 = – 10 + [( – 10 – ( – 84))] / 2 – 20 = + 7 dBm Spring 2010, Mar 11 . . .
ELEC 7770: Advanced VLSI Design (Agrawal) 50 What is Noise?
What Noise in an RF system is unwanted random fluctuations in a desired
Noise signal.
signal.
Noise is a natural phenomenon and is always present in the
Noise
environment.
environment.
Effects of noise: Interferes with detection of signal (hides the signal). Causes errors in information transmission by changing signal. Sometimes noise might imitate a signal falsely.
All communications system design and operation must account for
All
noise.
noise. Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 51 Describing Noise
Describing Consider noise as a random voltage or current
Consider
function, x(t), over interval – T/2 < t < T/2.
function,
Fourier transform of x(t) is XT(f). Power spectral density (PSD) of noise is power
Power
across 1Ω
across
Sx(f) = lim [ E{ XT(f)2 } / (2T) ]
(f)
lim
(2T) volts2/Hz T→∞
This is also expressed in dBm/Hz.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal)
52 Thermal Noise
Thermal Thermal (Johnson) noise: Caused by random movement
Thermal of electrons due to thermal energy that is proportional to
temperature.
temperature.
Called white noise due to uniform PSD over all
Called
frequencies.
frequencies.
Mean square open circuit noise voltage across R Ω
Mean
resistor [Nyquist, 1928]:
resistor
v2
=
4hfBR / [exp(hf/kT) – 1] Where Plank’s constant h = 6.626 × 1034 Jsec Frequency and bandwidth in hertz = f, B Boltzmann’s constant k = 1.38 × 10 – 23 J/K
Boltzmann’s Absolute temperature in Kelvin = T
53 Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) Problem to Solve
Problem Given that for microwave frequencies, hf << kT, derive
Given the following RayleighJeans approximation:
the
v2
=
4kTBR
Show that at room temperature (T = 290K), thermal noise
Show
power supplied by resistor R to a matched load is ktB or
– 174 dBm/Hz.
174
Noisy
resistor R
R Matched
load v = (4kTBR)1/2 Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 54 Other Noise Types
Other Shot noise [Schottky, 1928]: Broadband noise due to random
Shot behavior of charge carriers in semiconductor devices.
behavior
Flicker (1/f) noise: Lowfrequency noise in semiconductor devices,
Flicker
perhaps due to material defects; power spectrum falls off as 1/f. Can
be significant at audio frequencies.
be
Quantization noise: Caused by conversion of continuous valued
Quantization
analog signal to discretevalued digital signal; minimized by using
more digital bits.
more
Quantum noise: Broadband noise caused by the quantized nature of
Quantum
charge carriers; significant at very low temperatures (~0K) or very
high bandwidth ( > 1015 Hz).
high
Plasma noise: Caused by random motion of charges in ionized
Plasma
medium, possibly resulting from sparking in electrical contacts;
generally, not a concern.
generally, Spring 2010, Mar 11 . . .
55 ELEC 7770: Advanced VLSI Design (Agrawal) Measuring Noise
Measuring Expressed as noise power density in the units of dBm/Hz. Noise sources: Resistor at constant temperature, noise power = kTB W/Hz. Avalanche diode
Noise temperature: Tn = (Available noise power in watts)/(kB) kelvins Excess noise ratio (ENR) is the difference in the noise
Excess
output between hot (on) and cold (off) states, normalized to
reference thermal noise at room temperature (290K):
reference ENR = [k( Th – Tc )B]/(kT0B) = ( Th / T0) – 1
)B]/(kT Where noise output in cold state is takes same as reference. 10 log ENR ~ 15 to 20 dB
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 56 SignaltoNoise Ratio (SNR)
SignaltoNoise SNR is the ratio of signal power to noise power.
Si/Ni G Power (dBm) Input signal: low peak power,
good SNR G So/No
Output signal: high peak power,
poor SNR So/No Si/Ni
Noise floor Spring 2010, Mar 11 . . . Frequency (Hz)
ELEC 7770: Advanced VLSI Design (Agrawal) 57 Noise Factor and Noise Figure
Noise Noise factor (F) is the ratio of input SNR to output SNR: F = (Si /Ni) / (So /No)
= No / ( GNi ), when Si = 1W and G = gain of
DUT
DUT
= No /( kT0 BG), when Ni = kT0 B for input noise
source
source F≥1 Noise figure (NF) is noise factor expressed in dB: NF = 10 log F dB 0 ≤ NF ≤ ∞
Spring 2010, Mar 11 . . . 58
ELEC 7770: Advanced VLSI Design (Agrawal) Cascaded System Noise Factor
Cascaded Friis equation [Proc. IRE, July 1944, pp. 419 – 422]:
Fsys = F1 Gain = G1
Noise factor
= F1 Spring 2010, Mar 11 . . . F2 – 1
+ ———
G1 + Gain = G2
Noise factor
= F2 F3 – 1
Fn – 1
——— + · · · · + ———————
G1 G2
G1 G2 · · · Gn – 1 Gain = G3
Noise factor
= F3 ELEC 7770: Advanced VLSI Design (Agrawal) Gain = Gn
Noise factor
= Fn 59 Measuring Noise Figure: Cold
Noise Method
Noise Example: SOC receiver with large gain so noise output is
Example: measurable; noise power should be above noise floor of
measuring equipment.
measuring
Gain G is known or previously measured.
Noise factor, F = No / (kT0BG), where
(kT No is measured output noise power (noise floor) B is measurement bandwidth At 290K, kT0 = – 174 dBm/Hz Noise figure, NF = 10 log F
= No (dB) – ( – 174 dBm/Hz) – B(dB) – G(dB) This measurement is also done using Sparameters.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 60 Y – Factor
Factor Y – ffactor is the ratio of output noise in hot (power on) state to that
actor
in cold (power off) state.
in Y = Nh / N c = Nh / N 0 Y is a simple ratio. Consider, Nh = kThBG and Nc = kT0BG
kT Then Nh – Nc = kBG( Th – T0 ) or kBG = ( Nh – Nc ) / ( Th – T0 ) Noise factor, F =
Noise
=
Spring 2010, Mar 11 . . . = Nh /( kT0 BG) = ( Nh / T0 ) [ 1 / (kBG) ]
( Nh / T0 ) ( Th – T0 ) / (Nh – Nc )
ENR / (Y – 1) ELEC 7770: Advanced VLSI Design (Agrawal) 61 Measuring Noise Factor: Y – Factor Method
Measuring Noise source provides hot and cold noise power levels and is
Noise characterized by ENR (excess noise ratio).
characterized
Tester measures noise power, is characterized by its noise factor F2
and Yfactor Y2.
and Device under test (DUT) has gain G1 and noise factor F1. Twostep measurement: Calibration: Connect noise source to tester, measure output
Calibration:
power for hot and cold noise inputs, compute Y2 and F2.
power Measurement: Connect noise source to DUT and tester
Measurement:
cascade, measure output power for hot and cold noise inputs,
compute compute Y12, F12 and G1.
compute
12 and Use Friis equation to obtain F1.
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 62 Calibration
Calibration
Tester
(power meter)
F 2, Y2 Noise
source
ENR Y2 = Nh2 / Nc2, where Nh2 = measured power for hot source Nc2 = measured power for cold source
measured
c2 F2 = ENR / (Y2 – 1) Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 63 Cascaded System Measurement
Cascaded
Noise
source
ENR Tester
(power meter)
F 2, Y2 DUT
F1, Y1, G1
F12, Y12 Y12 = Nh12 / Nc12, where Nh12 = measured power for hot source Nc12 = measured power for cold source
measured
c12 F12 = ENR / ( Y12 – 1 ) G1 = ( Nh12 – Nc12 ) / ( Nh2 – Nc2 )
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 64 Problem to Solve
Problem Show that from noise measurements on a
Show
cascaded system, the noise factor of DUT is
given by
given
F2 – 1
F1 = F12 –
12 ———
———
G1 Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 65 Phase Noise
Phase Phase noise is due to small random variations in the phase of an
Phase RF signal. In time domain, phase noise is referred to as jitter.
jitter
Understanding phase:
δ amplitude
noise
t
φ
phase
noise V sin ωt ω
Frequency (rad/s)
Spring 2010, Mar 11 . . . t [V + δ(t)] sin [ωt + φ(t)] ω
Frequency (rad/s) ELEC 7770: Advanced VLSI Design (Agrawal) 66 Effects of Phase Noise
Effects Similar to phase modulation by a random signal. Two types: Long term phase variation is called frequency drift.
Long
frequency Short term phase variation is phase noise.
ort
phase Definition: Phase noise is the Fourier spectrum (power spectral
Definition:
density) of a sinusoidal carrier signal with respect to the carrier
power.
power.
L(f) = Pn /Pc (as ratio)
L(f)
= Pn in dBm/Hz – Pc in dBm (as dBc) Pn is RMS noise power in 1Hz bandwidth at frequency f
Pc is RMS power of the carrier Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 67 Phase Noise Analysis
Phase
[V + δ(t)] sin [ωt + φ(t)] = [V + δ(t)] [sin ωt cos φ(t) + cos ωt sin φ(t)]
≈ [V + δ(t)] sin ωt + [V + δ(t)] φ(t) cos ωt
Inphase carrier frequency with amplitude noise
White noise δ(t) corresponds to noise floor
Quadraturephase carrier frequency with amplitude and phase noise
Shortterm phase noise corresponds to phase noise spectrum Phase spectrum, L(f) = Sφ(f)/2
Where Sφ(f) is power spectrum of φ(t)
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 68 Phase Noise Measurement
Phase Phase noise is measured by low noise receiver
Phase
(amplifier) and spectrum analyzer:
(amplifier) Receiver must have a lower noise floor than the signal noise
Receiver Power (dBm) floor.
floor.
Local oscillator in the receiver must have lower phase noise
Local
than that of the signal. Signal spectrum Receiver phase noise
Receiver noise floor
Frequency (Hz) Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 69
69 Phase Noise Measurement
Phase Pure tone
Input
(carrier) DUT Hz offset
Spectrum analyzer power measurement
Power (dBm) over resolution bandwith (RBW)
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) carrier
70 Phase Noise Measurement Example
Phase Spectrum analyzer data: RBW = 100Hz Frequency offset = 2kHz Pcarrier = – 5.30 dBm Poffset = – 73.16 dBm
Poffset – Pcarrier – 10 log RBW Phase noise, L(f) = =
– 73.16 – ( – 5.30) – 10 log 100
=
– 87.86 dBc/Hz
87.86
Phase noise is specified as “ – 87.86 dBc/Hz at 2kHz
Phase
from the carrier.”
from
Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 71 Problem to Solve
Problem Consider the following spectrum analyzer data: RBW = 10Hz Frequency offset = 2kHz Pcarrier = – 3.31 dBm Poffset = – 81.17 dBm Determine phase noise in dBc/Hz at 2kHz from
Determine
the carrier.
the Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 72 References, Again
References,
1. S. Bhattacharya and A. Chatterjee, "RF Testing," Chapter 16, pages
S.
2.
3.
4.
5.
6. 745789, in System on Chip Test Archiitectures, edited by L.T. Wang,
tectures,
System
C. E. Stroud and N. A. Touba, Amsterdam: MorganKaufman, 2008.
C.
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for
M.
Digital, Memory & MixedSignal VLSI Circuits, Boston: Springer, 2000.
Digital,
J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC,
J.
and SiP Devices, Boston: Artech House, 2007.
and
B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey:
B.
RF
Upper
Prentice Hall PTR, 1998.
Prentice
J. Rogers, C. Plett and F. Dai, Integrated Circuit Design for HighJ.
Integrated
Speed Frequency Synthesis, Boston: Artech House, 2006.
K. B. Schaub and J. Kelly, Production Testing of RF and SystemonaK.
Production
Chip Devices for Wireless Communications, Boston: Artech House,
Boston:
2004.
2004. Spring 2010, Mar 11 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 73 ...
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