Unformatted text preview: 2 + (1 − X 2 ) ⋅ DH 2 T2 ≥ 0 + X 2 ⋅ DL 2 + (1 − X 2 ) ⋅ DH 2
Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 36 ILP – Constraints (cont.) DHi is the delay of gate i with high Vth
DLi is the delay of gate i with low Vth A second lookup table is constructed and specifies the delay for given gate type and fanout number. Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 37 ILP – Finding Critical Delay
Ti ≤ Tmax T can be specified or be the delay of longest path (Tc).
max To find Tc , we change constraints (2) to an equation, assigning all gates low Vth 0 ≤ Xi ≤1 Xi =1 Maximum Ti in the ILP solution is Tc. If we replace T with Tc , the objective function minimizes leakage power without sacrificing performance. Copyright Agrawal & Srivaths, 2007 max LowPower Design and Test, Lecture 5 38 PowerDelay Tradeoff
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Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 39 PowerDelay Tradeoff If we gradually increase Tmax from Tc , leakage power is further reduced, because more gates can be assigned high Vth .
But, the reduction trends to become slower.
When Tmax = (130%) Tc , the reduction about levels off because almost all gates are assigned high Vth . Maximum leakage reduction can be 98%. Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 40 Leakage & Dynamic Power Optimization 70nm CMOS c7552 Benchmark Circuit @ 90oC
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design LowPower Design and Test, Lecture 5 Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for PowerPerformance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp. 378387, December 2006. 41 Summary Leakage power is a significant fraction of the total power in nanometer CMOS devices.
Leakage power increases with temperature; can be as much as dynamic power.
Dual threshold design can reduce leakage. Reference: Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for PowerPerformance Tradeoff,” J. Low Power Electronics, Vol. 2, No. 3, pp. 378387, December 2006. Access other paper at http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 42 Problem: Leakage Reduction
Following circuit is designed in 65nm CMOS technology using low threshold transistors. Each gate has a delay of 5ps and a leakage current of 10nA. Given that a gate with high threshold transistors has a delay of 12ps and leakage of 1nA, optimally design the circuit with dualthreshold gates to minimize the leakage current without increasing the critical path delay. What is the percentage reduction in leakage power? What will the leakage power reduction be if a 30% increase in the critical path delay is allowed? Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 43 Solution 1: No Delay Increase Three critical paths are from the first, second and third inputs to the last output, shown by a dashed line arrow. Each has five gates and a delay of 25ps. None of the five gates on the critical path (red arrow) can be assigned a high threshold. Also, the two inverters that are on fourgate long paths cannot be assigned high threshold because then the delay of those paths will become 27ps. The remaining three inverters and the NOR gate can be assigned high threshold. These gates are shaded grey in the circuit.
The reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73%
Critical path delay = 25ps Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 44 Solution 2: 30% Delay Increase Several solutions are possible. Notice that any 3gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow.
The reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09%
Critical path delay = 29ps Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 45...
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