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Fourerdmgayandbwkernighanamplamodeling

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Unformatted text preview: Average 58%, Peak 68% Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 20 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993. M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183­188. V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10th Int’l Conf. VLSI Design, Jan. 1997, pp. 193­197. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12th Int’l Conf. VLSI Design, Jan. 1999, pp. 434­439. M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45­51. T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16th Int’l Conf. VLSI Design, Jan. 2003, pp. 527­532. T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” Proc. 18th Int’l Conf. VLSI Design, Jan. 2005, pp. 596­603. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 21 Components of Power Dynamic Signal transitions Logic activity Glitches Short­circuit Static Leakage Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 22 Subthreshold Conduction Ids Vgs – Vth -Vds I0 exp( ───── ) × (1– exp ── ) nVT VT = 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA Copyright Agrawal & Srivaths, 2007 Subthreshold region Ids Saturation region Sunthreshold slope Vth 0 0.3 0.6 0.9 1.2 Low-Power Design and Test, Lecture 5 1.5 1.8 V Vgs 23 Thermal Voltage, vT VT = kT/q = 26 mV, at room temperature. When Vds is several times greater than VT Ids Copyright Agrawal & Srivaths, 2007 = Vgs – Vth I0 exp( ───── ) nVT Low-Power Design and Test, Lecture 5 24 Leak...
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