Unformatted text preview: Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 31 Integer Linear Programming (ILP) to Minimize Leakage Power Use dualthreshold CMOS process
First, assign all gates low Vth Use an ILP model to find the delay (Tc) of the critical path
Use another ILP model to find the optimal Vth assignment as well as the reduced leakage power for all gates without increasing Tc Further reduction of leakage power possible by letting Tc increase Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 32 ILP Variables For each gate i define two variables. Ti : the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. Xi : a variable specifying low or high Vth for gate i ; Xi is an integer [0, 1], 1 gate i is assigned low Vth ,
0 gate i is assigned high Vth .
Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 33 ILP objective function Leakage power: Pleak = Vdd ∑ I leaki
i minimize the sum of all gate leakage currents, given by Min∑ ( X i ⋅ I Li + (1 − X i ) ⋅ I Hi )
i ILi is the leakage current of gate i with low Vth
IHi is the leakage current of gate i with high Vth
Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 34 ILP Constraints For each gate (1) Gate i Ti ≥ T j + X i ⋅ D Li + (1 − X i ) ⋅ D Hi Ti output of gate j is fanin of gate i (2) Gate j 0 ≤ Xi ≤1 Tj Max delay constraints for primary outputs (PO) (3) ≤ Tmax Ti Tmax is the maximum delay of the critical path
Copyright Agrawal & Srivaths, 2007 LowPower Design and Test, Lecture 5 35 ILP Constraint Example
0 1 2
3 Ti ≥ T j + X i ⋅ DLi + (1 − X i ) ⋅ DHi Assume all primary input (PI) signals on the left arrive at the same time. For gate 2, constraints are T2 ≥ T0 + X 2 ⋅ DL...
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 Fall '09
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 Gate, Trigraph, lowpower design, Copyright Agrawal, Srivaths

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