lp_hyd_5 - Low­Power Design and Test Gate­Level Power...

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Unformatted text preview: Low­Power Design and Test Gate­Level Power Optimization Vishwani D. Agrawal Auburn University, USA [email protected] Srivaths Ravi Texas Instruments India [email protected] Hyderabad, July 30­31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html Copyright Agrawal & Srivaths, 2007 Copyright Agrawal & Srivaths, 2007 Low­Power Design and Test, Lecture 5 1 Components of Power Dynamic Signal transitions Logic activity Glitches Short­circuit Static Leakage Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 2 Power of a Transition isc R VDD Dynamic Power Vo Vi = CLVDD2/2 + Psc CL R Ground Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 3 Dynamic Power Each transition of a gate consumes CV 2/2. Methods of power saving: Minimize load capacitances Transistor sizing Library­based gate selection Reduce transitions Logic design Glitch reduction Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 4 Glitch Power Reduction Design a digital circuit for minimum transient energy consumption by eliminating hazards Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 5 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition. Output logic state changes One transition is necessary Copyright Agrawal & Srivaths, 2007 Output logic state unchanged No transition is necessary Low-Power Design and Test, Lecture 5 6 Event Propagation Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew Path P1 1 0 13 P2 0 2 0 Copyright Agrawal & Srivaths, 2007 1 3 2 246 Path P3 5 Low-Power Design and Test, Lecture 5 7 Inertial Delay of an Inverter Vin dHL+dLH d = ──── dHL 2 dLH Vout time Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 8 Multi­Input Gate A DPD: Differential path delay Delay = d C B A DPD B C Copyright Agrawal & Srivaths, 2007 d d Hazard or glitch Low-Power Design and Test, Lecture 5 9 Balanced Path Delays A DPD Delay buffer Delay = d C B A B C Copyright Agrawal & Srivaths, 2007 d No glitch Low-Power Design and Test, Lecture 5 10 Glitch Filtering by Inertia A Delay ≥ DPD C B A DPD B d =DPD C Copyright Agrawal & Srivaths, 2007 Filtered glitch Low-Power Design and Test, Lecture 5 11 Theorem 2 Given that events occur at the input of a gate with inertial delay d at times, t1 ≤ . . . ≤ tn , the number of events at the gate output cannot exceed tn – t1 min ( n , 1 + -------min d ) tn - t 1 t1 Copyright Agrawal & Srivaths, 2007 t2 t3 tn Low-Power Design and Test, Lecture 5 time time 12 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - tj | < d Where ti and tj are arrival times of input Where events and d is the inertial delay of gate Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 13 Balanced Delay Method All input events arrive simultaneously Overall circuit delay not increased Delay buffers may have to be inserted 1 1 1 1 1 1 1 3 1 Copyright Agrawal & Srivaths, 2007 1 1 Low-Power Design and Test, Lecture 5 No increase in critical path delay 14 Hazard Filter Method Gate delay is made greater than maximum input path delay difference No delay buffers needed (least transient energy) Overall circuit delay may increase 1 1 1 1 1 Copyright Agrawal & Srivaths, 2007 1 1 1 1 3 Low-Power Design and Test, Lecture 5 15 Designing a Glitch­Free Circuit Maintain specified critical path delay. Glitch suppressed at all gates by Path delay balancing Glitch filtering by increasing inertial delay of gates A linear program optimally combines all objectives. Delay = d1 Delay = d2 Copyright Agrawal & Srivaths, 2007 |d1 – d2| < D D Low-Power Design and Test, Lecture 5 16 Benchmark Circuits Normalized Power Average Peak Circuit Max-delay (gates) No. of Buffers ALU4 7 15 5 0 0.80 0.79 0.68 0.67 C880 24 48 62 34 0.68 0.68 0.54 0.52 C6288 47 94 294 120 0.40 0.36 0.36 0.34 c7552 43 86 366 111 0.44 0.42 0.34 0.32 Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 17 Four­Bit ALU maxdelay Buffers inserted 7 10 12 15 5 2 1 0 Maximum Power Savings (zero-buffer design): Peak = 33 %, Average = 21 % Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 18 ALU4: Original and Low­Power Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 19 C7552 Circuit: Spice Simulation Power Saving: Average 58%, Peak 68% Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 20 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993. M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183­188. V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10th Int’l Conf. VLSI Design, Jan. 1997, pp. 193­197. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12th Int’l Conf. VLSI Design, Jan. 1999, pp. 434­439. M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45­51. T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16th Int’l Conf. VLSI Design, Jan. 2003, pp. 527­532. T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” Proc. 18th Int’l Conf. VLSI Design, Jan. 2005, pp. 596­603. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 21 Components of Power Dynamic Signal transitions Logic activity Glitches Short­circuit Static Leakage Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 22 Subthreshold Conduction Ids Vgs – Vth -Vds I0 exp( ───── ) × (1– exp ── ) nVT VT = 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA Copyright Agrawal & Srivaths, 2007 Subthreshold region Ids Saturation region Sunthreshold slope Vth 0 0.3 0.6 0.9 1.2 Low-Power Design and Test, Lecture 5 1.5 1.8 V Vgs 23 Thermal Voltage, vT VT = kT/q = 26 mV, at room temperature. When Vds is several times greater than VT Ids Copyright Agrawal & Srivaths, 2007 = Vgs – Vth I0 exp( ───── ) nVT Low-Power Design and Test, Lecture 5 24 Leakage Current Leakage current equals Ids when Vgs= 0 Leakage current, Ids = I0 exp(­Vth/nVT) At cutoff, Vgs = Vth , and Ids = I0 Lowering leakage to 10­bI0 Vth = bnVT ln 10 = 1.5b × 26 ln 10 = 90b mV Example: To lower leakage to I0/1,000 Vth = 270 mV Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 25 Threshold Voltage Vth = Vt0 + γ[(Φs+Vsb)½­ Φs½] Vt0 is threshold voltage when source is at body potential (0.4 V for 180nm process) Φs = 2VT ln(NA /ni ) is surface potential γ = (2qεsi NA)½tox /εox is body effect coefficient (0.4 to 1.0) NA is doping level = 8×1017 cm­3 ni = 1.45×1010 cm­3 Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 26 Threshold Voltage, Vsb = 1.1V Thermal voltage, VT = kT/q = 26 mV Φs = 0.93 V εox = 3.9×8.85×10­14 F/cm εsi = 11.7×8.85×10­14 F/cm tox = 40 Ao γ = 0.6 V½ Vth = Vt0 + γ[(Φs+Vsb)½­ Φs½] = 0.68 V Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 27 A Sample Calculation VDD = 1.2V, 100nm CMOS process Transistor width, W = 0.5μm OFF device (Vgs = Vth) leakage I0 = 20nA/μm, for low threshold transistor I0 = 3nA/μm, for high threshold transistor 100M transistor chip Power = (100×106/2)(0.5×20×10­9A)(1.2V) = 600mW for all low­threshold transistors Power = (100×106/2)(0.5×3×10­9A)(1.2V) = 90mW for all high­threshold transistors Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 28 Dual­Threshold Chip Low­threshold only for 20% transistors on critical path. Leakage power = 600×0.2 + 90×0.8 = 120 + 72 = 192 mW Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 29 Dual­Threshold CMOS Circuit Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 30 Dual­Threshold Design To maintain performance, all gates on the critical path are assigned low Vth . Most of the other gates are assigned high Vth . But, Some gates on non­critical paths may also be assigned low Vth to prevent those paths from becoming critical. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 31 Integer Linear Programming (ILP) to Minimize Leakage Power Use dual­threshold CMOS process First, assign all gates low Vth Use an ILP model to find the delay (Tc) of the critical path Use another ILP model to find the optimal Vth assignment as well as the reduced leakage power for all gates without increasing Tc Further reduction of leakage power possible by letting Tc increase Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 32 ILP ­Variables For each gate i define two variables. Ti : the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. Xi : a variable specifying low or high Vth for gate i ; Xi is an integer [0, 1], 1 gate i is assigned low Vth , 0 gate i is assigned high Vth . Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 33 ILP ­ objective function Leakage power: Pleak = Vdd ∑ I leaki i minimize the sum of all gate leakage currents, given by Min∑ ( X i ⋅ I Li + (1 − X i ) ⋅ I Hi ) i ILi is the leakage current of gate i with low Vth IHi is the leakage current of gate i with high Vth Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 34 ILP ­ Constraints For each gate (1) Gate i Ti ≥ T j + X i ⋅ D Li + (1 − X i ) ⋅ D Hi Ti output of gate j is fanin of gate i (2) Gate j 0 ≤ Xi ≤1 Tj Max delay constraints for primary outputs (PO) (3) ≤ Tmax Ti Tmax is the maximum delay of the critical path Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 35 ILP Constraint Example 0 1 2 3 Ti ≥ T j + X i ⋅ DLi + (1 − X i ) ⋅ DHi Assume all primary input (PI) signals on the left arrive at the same time. For gate 2, constraints are T2 ≥ T0 + X 2 ⋅ DL 2 + (1 − X 2 ) ⋅ DH 2 T2 ≥ 0 + X 2 ⋅ DL 2 + (1 − X 2 ) ⋅ DH 2 Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 36 ILP – Constraints (cont.) DHi is the delay of gate i with high Vth DLi is the delay of gate i with low Vth A second look­up table is constructed and specifies the delay for given gate type and fanout number. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 37 ILP – Finding Critical Delay Ti ≤ Tmax T can be specified or be the delay of longest path (Tc). max To find Tc , we change constraints (2) to an equation, assigning all gates low Vth 0 ≤ Xi ≤1 Xi =1 Maximum Ti in the ILP solution is Tc. If we replace T with Tc , the objective function minimizes leakage power without sacrificing performance. Copyright Agrawal & Srivaths, 2007 max Low-Power Design and Test, Lecture 5 38 Power­Delay Tradeoff 1 0.9 N ormalized Leakage Pow er 0.8 C 432 0.7 C 880 0.6 C 1908 0.5 0.4 0.3 0.2 0.1 1 1.1 1.2 1.3 1.4 1.5 N ormalized C ritical Path D elay Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 39 Power­Delay Tradeoff If we gradually increase Tmax from Tc , leakage power is further reduced, because more gates can be assigned high Vth . But, the reduction trends to become slower. When Tmax = (130%) Tc , the reduction about levels off because almost all gates are assigned high Vth . Maximum leakage reduction can be 98%. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 40 Leakage & Dynamic Power Optimization 70nm CMOS c7552 Benchmark Circuit @ 90oC 900 700 600 500 400 300 200 100 0 Leakage power Dynam ic power Tot al power Le ex aka d cee ge yn d po am s we ic r Micr owat t s 800 Or iginal cir cuit Copyright Agrawal & Srivaths, 2007 Opt im ized design Low-Power Design and Test, Lecture 5 Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power­Performance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp. 378­387, December 2006. 41 Summary Leakage power is a significant fraction of the total power in nanometer CMOS devices. Leakage power increases with temperature; can be as much as dynamic power. Dual threshold design can reduce leakage. Reference: Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power­Performance Tradeoff,” J. Low Power Electronics, Vol. 2, No. 3, pp. 378­387, December 2006. Access other paper at http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 42 Problem: Leakage Reduction Following circuit is designed in 65nm CMOS technology using low threshold transistors. Each gate has a delay of 5ps and a leakage current of 10nA. Given that a gate with high threshold transistors has a delay of 12ps and leakage of 1nA, optimally design the circuit with dual­threshold gates to minimize the leakage current without increasing the critical path delay. What is the percentage reduction in leakage power? What will the leakage power reduction be if a 30% increase in the critical path delay is allowed? Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 43 Solution 1: No Delay Increase Three critical paths are from the first, second and third inputs to the last output, shown by a dashed line arrow. Each has five gates and a delay of 25ps. None of the five gates on the critical path (red arrow) can be assigned a high threshold. Also, the two inverters that are on four­gate long paths cannot be assigned high threshold because then the delay of those paths will become 27ps. The remaining three inverters and the NOR gate can be assigned high threshold. These gates are shaded grey in the circuit. The reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73% Critical path delay = 25ps Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 44 Solution 2: 30% Delay Increase Several solutions are possible. Notice that any 3­gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow. The reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09% Critical path delay = 29ps Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 45 ...
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This note was uploaded on 09/16/2011 for the course ELEC 4944 taught by Professor Staff during the Fall '09 term at Auburn University.

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