Lp_hyd_5

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Unformatted text preview: 2 Given that events occur at the input of a gate with inertial delay d at times, t1 ≤ . . . ≤ tn , the number of events at the gate output cannot exceed tn – t1 min ( n , 1 + -------min d ) tn - t 1 t1 Copyright Agrawal & Srivaths, 2007 t2 t3 tn Low-Power Design and Test, Lecture 5 time time 12 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - tj | < d Where ti and tj are arrival times of input Where events and d is the inertial delay of gate Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 13 Balanced Delay Method All input events arrive simultaneously Overall circuit delay not increased Delay buffers may have to be inserted 1 1 1 1 1 1 1 3 1 Copyright Agrawal & Srivaths, 2007 1 1 Low-Power Design and Test, Lecture 5 No increase in critical path delay 14 Hazard Filter Method Gate delay is made greater than maximum input path delay difference No delay buffers needed (least transient energy) Overall circuit delay may increase 1 1 1 1 1 Copyright Agrawal & Srivaths, 2007 1 1 1 1 3 Low-Power Design and Test, Lecture 5 15 Designing a Glitch­Free Circuit Maintain specified critical path delay. Glitch suppressed at all gates by Path delay balancing Glitch filtering by increasing inertial delay of gates A linear program optimally combines all objectives. Delay = d1 Delay = d2 Copyright Agrawal & Srivaths, 2007 |d1 – d2| < D D Low-Power Design and Test, Lecture 5 16 Benchmark Circuits Normalized Power Average Peak Circuit Max-delay (gates) No. of Buffers ALU4 7 15 5 0 0.80 0.79 0.68 0.67 C880 24 48 62 34 0.68 0.68 0.54 0.52 C6288 47 94 294 120 0.40 0.36 0.36 0.34 c7552 43 86 366 111 0.44 0.42 0.34 0.32 Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 17 Four­Bit ALU maxdelay Buffers inserted 7 10 12 15 5 2 1 0 Maximum Power Savings (zero-buffer design): Peak = 33 %, Average = 21 % Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 18 ALU4: Original and Low­Power Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 19 C7552 Circuit: Spice Simulation Power Saving:...
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This note was uploaded on 09/16/2011 for the course ELEC 4944 taught by Professor Staff during the Fall '09 term at Auburn University.

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