7770project Xi Qian&Lixing Zhao

7770project Xi Qian&Lixing Zhao - Advanced VLSI...

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Advanced VLSI Design Final Project Verilog HDL Based Simulation of Process Variance Among Integrated Circuits Xi Qian, Lixing Zhao 1. Background and Introduction In IC manufacturing, flaws are supposed to emerge randomly. If same or familiar failures keep on showing up, it’s highly likely that certain site(s) on chip suffer systematical vulnerability through fabrication processes, and local layout and/or routing should be redone to improve the yield. To pinpoint a problematical site, small delay tests and diagnosis must be conducted and results compared with those from simulations. Path delays consist of two parts: a systematical component and a random component. The former is viewed stable for one chip and its adjacent neighbors on wafer, and the latter varies within a range upon every operation. Most simulation methods, such as SPICE, suffer insufficiency in mimicry of this random component, thus fail in bringing about statistical delay information. Moreover, process variances are hard simulate, thus handicapping the approximation to factual cases. This report involves partial work of relative ranking research, which aims to small delay fault diagnosis and requires for capability in generating statistical delay information referring not only random delay components but also process variances. We use ISCAS89 benchmarks for analysis, and all types of logic gates involved are rewritten into new styles and benchmarks are modified into equivalent combinational-logic circuits for easier LOS (launch on shift) or LOC (launch on capture) test pattern application. The structure of this report is as follow: Sections 2 and 3 explains and exemplify our descriptions and tests of basic gates; Section 4 shows the modification of benchmarks containing delay information; Section 5 provides the test bench for modified benchmark and related simulation is conducted; Section 6 gives conclusions. 2. Remodeling Basic Gates In CAD design, HDL codes are mapped onto certain technologies upon synthesis, and these technology libraries contain various basic cells/gates. We use ISCAS89 benchmarks here, which include up to 13 types of combinational gates, namely NOT, 2/3/4 input NOR/NAND/OR/AND gates. By remodeling these basic gates into a new description style that delay parameters can be specified, we then substitute all original gates in benchmarks with new gates without changing the logic function. (1) NOT Gate (inverter) Inverters are the most essential structure of CMOS technology. See 1
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Advanced VLSI Design Final Project in figure on the right. We assume that ideally, the W/L ratios of PMOS and NMOS are manipulated to achieve balanced rising and falling delays. We also assume that the random component would be no more than 10% of the systematical component. Thus a new description is as follow, where we specify systematical components of both rising and falling time as 100 which bears no unit: -----------------------------inverter--------------------------- module not_gate (dout,din);
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7770project Xi Qian&Lixing Zhao - Advanced VLSI...

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