Allani_Report

Allani_Report - 1 Mridula Allani Spring, 2010 gate length...

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Abstract With the reduction of MOSFET dimensions, the manufacturing process variations have been increasing in the CMOS technology. For example, the intra-die variations in channel length were observed to be 35% of total variations in 130nm CMOS and 60% in 70nm CMOS [5]. The variations in the impurity doping concentrations, oxide thickness, temperature, channel length and other process parameters affect the electrical parameters such as delay, node capacitances, threshold and currents in the transistors. In this project, I have studied the effect of threshold voltage variations on the delay, dynamic power and leakage power in a two-bit ripple carry adder. Monte Carlo Analysis has been used to simulate the variations in 45nm and 32nm CMOS technology. Index Terms — Dynamic Power, Leakage Power, Critical Path Delay, Monte Carlo Analysis, Process Variations, Threshold Voltage, 3-sigma Deviation. I. INTRODUCTION Power and performance are the most important design considerations for the digital designers. Various design techniques have been developed to optimize power and performance for electronic circuits. The threshold voltage, oxide thickness, and the channel length are the most important parameters that effect the power consumed by a device and its speed of operation. These parameters are now subject to stochastic variations induced by the semiconductor process and hence, is largely impacting the device operation. The semi-conductor manufacturing process induces some variations in the physical parameters of the MOS devices which in turn induce variations in the electrical parameters of the devices. These variations are statistical in nature. Due to shrinking of technology node these process variations are introducing very drastic variations in the electrical properties of the MOSFETs and thereby affecting its performance and power distribution. The parameters that get affected are, but not limited to, the doping concentrations, the oxide thickness, the . gate length and width, the threshold voltage, the channel length, propagation delay and power dissipation. According to authors of [3], the variation in threshold voltage for a 45nm CMOS process is about 42% and the variations in channel length is about 10%. Authors of [5] quote that the intra-die variations in channel length were observed to be 35% of total variations in 130nm CMOS and 60% in 70nm CMOS. It is observed that there is an increasing trend in the variations with decreasing
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Allani_Report - 1 Mridula Allani Spring, 2010 gate length...

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