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Unformatted text preview: Study synchronization in asynchronously communicating digital systems Surgnier Characterize inverter and 2-input NAND gates for delay and leakage (below 180nm technologies) Venkataramani Design and evaluate a clock distribution network for s5378 benchmark circuit Venkatasubramanian Study operation of flip flop at sub-threshold region in 90 nm technology Zhao Study correlation of delay defects to hazards on critical paths...
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- Spring '08