Farhana - Farhana Rashid Email id: fzr0001@auburn.edu 1...

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Farhana Rashid Email id: fzr0001@auburn.edu Abstract —Fault equivalence is used to collapse the fault sets in combinational circuits. The ATPG then randomly selects a fault from each group of equivalent fault sets and generates test vectors accordingly. In this project we have examined the variations in test generation time of every fault in a equivalent fault group and observed that we can get a significant test pattern generation time variation if the chosen fault sites takes minimum time to generate test vectors. Index Terms —fault simulation, equivalent faults, ATPG, HITEC/PROOFS. I. INOTRODUCTION quivalent faults are used to collapse the fault list in combinational circuits. The collapsed fault list is then used to generate the test vectors to test the circuit for stuck at faults. The effect of equivalent faults on test pattern generation time is examined exhaustively using HITEC/PROOF on ISCAS85 Benchmark circuits. The result shows that there is a time variation which depends on the fault chosen from the equivalent fault set to generate the test pattern. E II.P ROCEDURE A ND S IMULATED D ATA A.Procedure To examine the equivalent fault sets exhaustively , ISCAS85 bench mark circuits were simulated using HITEC/PROOFS package. HITEC/PROOFS is a gate level,sequential circuit test generation and fault simulation package which targets single stuck at faults. Fault lists are automatically generated for all single stuck at faults in the circuit. Individual faults are targeted by HITEC and when a successful test vector is generated to detect a target fault HITEC invokes PROOFS fault simulator to find the test coverage. Here I have used the HITEC/PROOFS package on combinational circuits . Among the ISCAS85 circuits c7552 was used for examining the equivalent fault sets as this circuit has the largest number of fault sites in it's gate level description . a C7552 is a a 34-bit adder and magnitude comparator with input parity checking functionality. It has 207 inputs,108 outputs and 3512 gates. This benchmark circuit contains a 34-bit adder, a 34-bit
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Farhana - Farhana Rashid Email id: fzr0001@auburn.edu 1...

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