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hw1prob - Problem 3 Synthesize the 16-bit adder design for...

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ELEC 7770-001, Spring 2010 Homework # 1 Problems Assigned: Wednesday, Feb 3, 2010 Due: Wednesday, Feb 17, 2010 Problem 1: Determine whether or not two benchmark circuits, c499 and c1355, are functionally equivalent. Problem 2: Implement a 16-bit ripple carry adder with a carry input in 0.18 micron CMOS technology. Find its critical path delay using a static timing analyzer (STA). Write an input vector pair that will activate the critical path. Simulate the circuit using either an event-driven timing simulator or the spice simulator to verify the result of STA.
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Unformatted text preview: Problem 3: Synthesize the 16-bit adder design for minimum area and minimum delay options using an automatic synthesis program. Simulate the two designs for the vector pair generated in Problem 2. Does this vector pair activate critical paths in the two designs? Problem 4: Use an ATPG program to determine whether all three designs done in Problems 2 and 3 are irredundant. Tabulate the data on number of gates, critical path delay and redundancy for your designs. . ELEC7770 Homework 3 Problems Page 1 of 1...
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