Unformatted text preview: Problem 3: Synthesize the 16-bit adder design for minimum area and minimum delay options using an automatic synthesis program. Simulate the two designs for the vector pair generated in Problem 2. Does this vector pair activate critical paths in the two designs? Problem 4: Use an ATPG program to determine whether all three designs done in Problems 2 and 3 are irredundant. Tabulate the data on number of gates, critical path delay and redundancy for your designs. . ELEC7770 Homework 3 Problems Page 1 of 1...
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- Spring '08
- Critical path, critical path delay, 16-bit adder design, input vector pair