This preview shows page 1. Sign up to view the full content.
Unformatted text preview: rules. (d) Sketch the circuit with flip-flops. Problem 2: An output buffer has an input capacitance of 250fF and a load capacitance of 100pF. How many inverters are required in a fixed-taper design to minimize the propagation delay? What are the capacitances of those stages? What is the total delay the buffer contributes if 100ps is the delay of the gate driving the buffer? Hint: Besides class notes, the following references may be helpful: 1.H. C. Lin and L. Linholm, An Optimized Output Stage for MOS Integrated Circuits, IEEE Jour. Solid State Circuits , vol. SC-10, no. 2, pp. 106-109, April 1975. 2.J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails , IEEE Press, Wiley-Interscience, 2004, pp. 116-118. ELEC7770 Homework 3 Problems Page 1 of 1...
View Full Document
- Spring '08