# hw3prob - rules(d Sketch the circuit with flip-flops...

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ELEC 7770-001, Spring 2010 Homework # 3 Problems Assigned: Wednesday, March 22, 2010 Due: Wednesday, April 5, 2010 Problem 1: A ripple carry adder is made of full adder cells each having 1 unit of combinational delay. To convert a four-bit ripple carry adder into a four stage pipeline adder proceed as following: (a) Consider the original adder as a one-stage pipeline with clock period of 4 time units. Construct the retiming graph. Note the critical path delay is 4 units. (b) To model a four stage pipeline that will have a latency of four clock cycles, insert four clock delays on the edge that connects the output node to host. (c) Retime the graph such that the longest combinational path has one unit of delay. This can be done either by solving the constraint set problem or by moving the clock delays according to retiming
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Unformatted text preview: rules. (d) Sketch the circuit with flip-flops. Problem 2: An output buffer has an input capacitance of 250fF and a load capacitance of 100pF. How many inverters are required in a fixed-taper design to minimize the propagation delay? What are the capacitances of those stages? What is the total delay the buffer contributes if 100ps is the delay of the gate driving the buffer? Hint: Besides class notes, the following references may be helpful: 1.H. C. Lin and L. Linholm, “An Optimized Output Stage for MOS Integrated Circuits,” IEEE Jour. Solid State Circuits , vol. SC-10, no. 2, pp. 106-109, April 1975. 2.J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails , IEEE Press, Wiley-Interscience, 2004, pp. 116-118. ELEC7770 Homework 3 Problems Page 1 of 1...
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## This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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