# hw3sol - ELEC 7770-001 Spring 2010 Homework 3 Solution...

This preview shows pages 1–2. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ELEC 7770-001, Spring 2010 Homework # 3 Solution Assigned: Wednesday, March 22, 2010 Due: Wednesday, April 5, 2010 Problem 1: A ripple carry adder is made of full adder cells each having 1 unit of combinational delay. To convert a four-bit ripple carry adder into a four stage pipeline adder proceed as following: (a) Consider the original adder as a one-stage pipeline with clock period of 4 time units. Construct the retiming graph. Note the critical path delay is 4 units. (b) To model a four stage pipeline that will have a latency of four clock cycles, insert four clock delays on the edge that connects the output node to host. (c) Retime the graph such that the longest combinational path has one unit of delay. This can be done either by solving the constraint set problem or by moving the clock delays according to retiming rules. (d) Sketch the circuit with flip-flops. Solution: (a) The original ripple carry adder and its retiming graph are shown below. Critical path delay is 4 units and (a) The original ripple carry adder and its retiming graph are shown below....
View Full Document

{[ snackBarMessage ]}

### Page1 / 3

hw3sol - ELEC 7770-001 Spring 2010 Homework 3 Solution...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online